CS7808 datasheet(23/52 Pages) CIRRUS

23 / 52 page

CS7808

4. MEMORY MAP

4.1

Processor Memory Map

The CS7808 externally supports up to 32 Mbytes

DRAM and 16 Mbytes ROM/NVRAM. Table 10,

Table 11 and Table 12 on the next page list the

memory map as viewed by the RISC processors,

and identifies whether each segment is mapped or

cacheable.

For detailed information on programming CS7808

memory, see CS7808 Memory Interface User’s

Manual (DS525UMD1).

4.2

Host Port Memory Map

Table 11onpage 23 lists the memory map as

viewed by host slave port.

4.3

Internal I/O Space Map

Table 10, Table 11, and Table 12 show how the In-

ternal I/O space is mapped between general regis-

ters,

internal

SRAM

ports,

and

the

RISC

processors’ debug port.

Processor Byte Address

Description

Cacheable

0000_0000 – 07FF_FFFF

DRAM (mapped)

8000_0000 - 81FF_FFFF

DRAM (32 Mbytes)

9400_0000 – 9CFF_FFFF

16-bit NVRAM write (16 Mbytes)

9C00_0000 – 9CFF_FFFF

16-bit NVRAM/ROM (16 Mbytes)

9D00_0000 – 9DFF_FFFF

8-bit NVRAM/ROM (16 Mbytes)

A000_0000 – A1FF_FFFF

DRAM (32 Mbytes)

B000_0000 – B003_FFFF

Internal I/O (256 Kbytes)

B400_0000 – BCFF_FFFF

16-bit NVRAM write (16 Mbytes)

BC00_0000 – BCFF_FFFF

16-bit NVRAM/ROM (16 Mbytes)

BD00_0000 – BDFF_FFFF

8-bit NVRAM/ROM (16 Mbytes)

C000_0000 – FFFF_FFFF

DRAM (mapped)

Table 10. Memory Map-RISC0 Processor

Host Byte Address

Description

0000 0000 – 003F FFFF

Internal I/O Space

1000 0000 – 13FF FFFF

DRAM space (16 Mbytes)

1400 0000 – 17FF FFFF

NVRAM space (16 Mbytes)

Table 11. Host Port Memory Map

Byte Address Offset

Description

0_0000 – 0_2FFF

General registers

0_3000 – 1_FFFF

General Internal SRAM

2_0000 – 2_FFFF

RISC_0 Internal SRAM/Registers

3_0000 – 3_FFFF

RISC_1 Internal SRAM/Registers

Table 12. Internal I/O Space Map

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