WM8510GEDSSLASHV datasheet(34/56 Pages) WOLFSON

34 / 56 page

WM8510

Product Preview

PP Rev 1.2 December 2004

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R49

VROI

VREF (AVDD/2 or 1.5xAVDD/2) to

analogue output resistance

0: approx 1k

Ω

1: approx 30 k

Ω

Table 20 Disabled Outputs to VREF Resistance

A dedicated buffer is available for tieing off unused analogue I/O pins as shown in Figure 16. This

buffer can be enabled using the BUFIOEN register bit.

If the SPKBOOST or MONOBOOST bits are set then the relevant outputs will be tied to the output of

the DC level shift buffer at 1.5xAVDD/2 when disabled.

Table 21 summarises the tie-off options for the speaker and mono output pins.

Figure 16 Unused Input/Output Pin Tie-off Buffers

MONOEN/

SPKN/PEN

MONOBOOST/

SPKBOOST

VROI

OUTPUT CONFIGURATION

1kΩ tieoff to AVDD/2

30kΩ tieoff to AVDD/2

1kΩ tieoff to 1.5xAVDD/2

30kΩ tieoff to 1.5xAVDD/2

Output enabled (DC level=AVDD/2)

Output enabled (DC level=1.5xAVDD/2)

Table 21 Unused Output Pin Tie-off Options

OUTPUT SWITCH

When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch

control input to automatically disable the speaker outputs and enable the mono output. For example

when a line is plugged into a jack socket. In this mode, enabled by setting GPIOSEL=001, pin

CSB/GPIO switches between mono and speaker outputs (e.g. when pin 12 is connected to a

mechanical switch in the headphone socket to detect plug-in). The GPIOPOL bit reverses the polarity

of the CSB/GPIO input pin.

WM8510GEDS/V bảng dữ liệu(PDF) 34 Page - Wolfson Microelectronics plc

WM8510GEDS/V bảng dữ liệu(HTML) 34 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL