LM9627 datasheet(33/37 Pages) NSC

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Timing Information (continued)

2.0

DIGITAL VIDEO PORT SLAVE MODE TIMING

Figure 54. Slave Mode Row Trigger and Readout Timing

Figure 55. Slave Mode d[11:0], hsync & vsync to pclk Timing

Figure 56. Rising Edge of mclk to Valid Pixel Data

The following specifications apply for all supply pins = +3.0V & CL = 10pF unless otherwise noted. Boldface limits apply for TA =

TMIN to TMAX: all other limits TA = 25

oC (Note 7)

Label

Descriptions

Min

Typ

Max

Pulse width of row trigger

* mclk

First pixel out after rising edge of row trigger

124 * mclk

Minimum time between row triggers.

780 * mclk

Max time to assert next frame trigger after last row

trigger.

96 * mclk

Pulse width of Frame trigger

* mclk

Time to valid pixel data after rising edge of mclk

44ns

hsync

d[11:0]

mclk

P652

P653

P654

P655

P640

P652

P653

P654

Row n-1

Row n

trigger row n

trigger row n+1

vsync

hsync

trigger last row

mclk

trigger Frame n+1

in frame n

d[11:0]

mclk

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