ACT8870 datasheet(29/38 Pages) ACTIVE-SEMI

29 / 38 page

ACT8870QJ-T

REV 0 23-DEC-2016

Innovative PowerTM

ActiveSwitcherTM is a trademark of Active-Semi.

the LDO limits the output current which causes the out-

put voltage to drop. This can result in an undervoltage

fault in addition to the current limit fault. If an LDO

reaches current limit protection, the status is reported in

the ILIM_REG[x] I2C registers. The contents of these

registers are latched until read via I2C. When the cur-

rent limiting results in a drop in output voltage that trig-

gers an undervoltage condition, the IC shuts down all

power supplies, asserts IRQ low, and enters the

UVLOFLT state. The IC restarts in 100ms and starts up

with default sequencing. Overcurrent and short circuit

conditions

can

masked

via

the

I2C

bit

LDOx_ILIM_FLTMSK.

Input Capacitor Selection

Each LDO requires a high quality, low-ESR, ceramic

input capacitor. A 1uF is typically suitable, but this value

can be increased without limit. The input capacitor is

should be a X5R, X7R, or similar dielectric.

Output Capacitor Selection

Each LDO requires a high quality, low-ESR, ceramic

output capacitor. A 1uF is typically suitable, but this

value can be increased without limit. The input capacitor

is should be a X5R, X7R, or similar dielectric.

PC board layout guidance

Proper parts placement and PCB layout are critical to

the operation of switching power supplies. Follow the

following layout guidelines when designing the

ACT8870 PCB. Refer to the Active-Semi ACT8870

Evaluation Kits for layout examples

1. Place the buck input capacitors as close as possible

to the IC. Connect the capacitors directly to the

corresponding VIN_Bx input pin and PGNDx power

ground pin. Avoid the use of vias if possible.

2. Minimize the switch node trace length between

each SW_Bx pin and the inductor. Avoid routing

sensitive analog signals near these high frequency,

high dV/dt traces.

3. Place the LDO input capacitors close to their input

pins. Connect their ground pins into the ground

plane that connects the IC’s exposed pad.

4. The input capacitor and output capacitor grounds

should be connected as close together as possible,

with short, direct, and wide traces.

5. Connect the PGNDx ground pins and the AGND

ground pin directly to the exposed pad under the IC.

The AGND ground plane should be routed

separately from the other ground planes and only

connect to the main ground plane under the IC at

the AGND pin.

6. Connect the VIO_IN input capacitor to the AGND

ground pin.

7. Connect the VIN input capacitor to the AGND

ground pin.

8. Remember that all open drain outputs need pullup

resistors.

9. Connect the exposed pad directly the top layer

ground plane. Connect the top layer ground plane

to both internal ground planes and the PCB

backside ground plane with thermal vias. Provide

ground plane routing on multiple layers that allows

the IC’s heat to flow into the PCB and then spread

radially from the IC. Avoid cutting the ground planes

and adding vias that restrict the radial flow of heat.of

operating conditions, and are relatively insensitive

to layout considerations.

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