ACT8870 datasheet(22/38 Pages) ACTIVE-SEMI

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ACT8870QJ-T

REV 0 23-DEC-2016

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power up sequence. The regulators are not sequenced

when entering ACTIVE from SLEEP.

SLEEP State

The SLEEP state is a low power mode for the operating

system. Each output can be programmed to be on or off

in the SLEEP state. The outputs do not follow any se-

quencing when turning on or off as they enter or exit the

SLEEP state. They do turn on with their programmed

softstart time. Buck1/2/3/4 can be programmed to regu-

late to their VSET0 voltage, VSET1 voltage, or be

turned off in the SLEEP state. LDO1/2/3 can be pro-

grammed to regulate to their VSET0 voltage or can be

programmed to be turned off. Note that LDO1/2/3 do

not have a VSET1 voltage.

The IC can enter SLEEP via a hardware input pin or an

I2C command.

The hardware input is typically the

PWREN pin, but this can be reconfigured to other pins.

To enable SLEEP via I2C, program the following:

Set register 0x08h bit1 (PWR_DN_MODE) = 1

Set register 0x00h bit0 (PWRDN_EN) = 1

To enter SLEEP, program register 0x01h bit1

(SLP_ENTR) = 1.

I2C is disabled in SLEEP mode, to the only way to exit

SLEEP mode is to toggle the PWREN pin.

THERMAL State

In the THERMAL state the chip has exceeded the ther-

mal shutdown temperature. To protect the device, all

the regulators are shut down and all three nRESETx

pins are asserted low. This state can be disabled by set-

ting register 0x0Ah bit4 (TSD_nMASK) = 0. Note that

thermal shutdown fault flag, TSD_SHUTDWN, still pro-

vides the thermal status even TSD_nMASK = 0.

OVUVFLT State

In the OVUVFLT state one of the regulators has exceed

an OV level at any time or UV level after the soft start

ramp has completed. All regulators shutdown and all

three nRESETx outputs are asserted low when the IC

enters OVUVFLT state. The OVUVFLT state is timed to

retry after 100ms and enter the ACTIVE state. If the OV

or UV condition still exists in the ACTIVE state the IC

returns back to the OVUVFLT state. The cycle contin-

ues until the OV or UV fault is removed or the input

power is removed. This state can be disabled by setting

the OV_nMASK or UV_nMASK non-volatile bits low.

The IC does not directly enter OVUVFLT in an overcur-

rent condition, but does enter this state due to the re-

sulting UV condition.

Figure 3. State Machine

Sequencing

The ACT8870 provides the end user with extremely

versatile sequencing capability that can be optimized for

many different applications. Each of the seven outputs

has four basic sequencing parameters: input trigger,

turn-on delay, softstart time, and output voltage. Each of

these parameters is controlled via the ICs internal

registers. As an example, the ACT8870QJ101-T

sequencing and output voltages are optimized for the

Atmel SAMA5D3D3 processor. The specifics for this IC

as well as others are detailed at the end of the datasheet.

Contact sales@active-semi.com for custom sequencing

configurations. Refer to the Active-Semi Application

Note describing the Register Map for full details on I2C

functionality and programming ranges.

Input trigger. The input trigger for a regulator is the

event that turns that regulator on. Each output can have

a separate input trigger. The input trigger can be the

internal power ok (POK) signal from one of the other

regulators, the internal VIN POK signal, or an external

signal applied to an input pin such as EXT_PG or GPIO.

This flexibility allows a wide range of sequencing

possibilities, including have some of the outputs be

sequenced with another external power supply or a

control signal from the host. As an example, if the LDO1

input trigger is Buck1, LDO1 will not turn on until Buck1

is in regulation. Input triggers are defined at the factory

and can only be changed with a custom CMI

configuration. The nRESETx, POK, PG, and EXT_EN

outputs can be connected to a power supply’s internal

POK signal and used to trigger external supplies in the

overall sequencing scheme.

Turn-on Delay. The turn-on delay is the time between

an input trigger going active and the output starting to

turn on. Each output’s turn-on delay is configured via its

I2C bit ONDLY. Turn-on delays can be changed after the

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