AD9144-EBZ datasheet(43/126 Pages) AD

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AD9144

Data Sheet

Rev. A | Page 42 of 125

To avoid this common-mode current draw, a 50% duty-cycle

periodic SYSREF± signal can be used with ac coupling capacitors.

If ac-coupled, the ac coupling capacitors combine with the

resistors shown in Figure 45 to make a high-pass filter with RC

time constant τ = RC. Select C such that τ > 4/SYSREF Freq.

In addition, the edge rate must be sufficiently fast—at least

1.3 V/ns is recommended per Table 5—to meet the SYSREF vs.

DAC clock keep out window (KOW) requirements.

It is possible to use ac-coupled mode without meeting the

frequency to time-constant constraint mentioned by using

SYSREF hysteresis (Register 0x081 and Register 0x082).

However, this increases the DAC clock KOW (Table 5 does not

apply) by an amount depending on SYSREF frequency, level of

hysteresis, capacitor choice, and edge rate.

3kΩ

~600mV

1.2V

SYSREF+

SYSREF–

3kΩ

Figure 45. SYSREF± Input Circuit

Sync Processing Modes Overview

The AD9144 supports various LMFC sync processing modes.

These modes are one-shot, continuous, windowed continuous,

and monitor modes. All sync processing modes perform a

phase check to see that the LMFC is phase aligned to an

alignment edge. In Subclass 1, the SYSREF pulse acts as the

alignment edge; in Subclass 0, an internal processing clock acts

as the alignment edge. If the signals are not in phase, a clock

rotation occurs to align the signals. The sync modes are

described in the following sections. See the Sync Procedure

section for details on the procedure for syncing the LMFC

signals.

One-Shot Sync Mode (SYNCMODE = 0x1)

In one-shot sync mode, a phase check occurs on only the first

alignment edge that is received after the sync machine is armed.

If the phase error is larger than a specified window error

tolerance, a phase adjustment occurs. Though an LMFC

synchronization occurs only once, the SYSREF signal can

still be continuous.

Continuous Sync Mode (SYNCMODE = 0x2)

Continuous mode must only be used in Subclass 1 with a periodic

SYSREF± signal. In continuous mode, a phase check/alignment

occurs on every alignment edge.

Continuous mode differs from one-shot mode in two ways.

First, no SPI cycle is required to arm the device; the alignment

edge seen after continuous mode is enabled results in a phase

check. Second, a phase check (and when necessary, clock rotation)

occurs on every alignment edge in continuous mode. The one

caveat to the previous statement is that when a phase rotation cycle

is underway, subsequent alignment edges are ignored until the

logic lane is ready again.

The maximum acceptable phase error (in DAC clock cycles)

between the alignment edge and the LMFC edge is set in the

error window tolerance register. If continuous sync mode is

used with a nonzero error window tolerance, a phase check

occurs on every SYSREF pulse, but an alignment occurs only if

the phase error is greater than the specified error window

tolerance. If the jitter of the SYSREF± signal violates the KOW

specification given in Table 5 and therefore causes phase error

uncertainty, the error tolerance can be increased to avoid

constant clock rotations. Note that this means the latency is less

deterministic by the size of the window. If the error window

tolerance must be set above 3, Subclass 0 with a one-shot sync is

recommended.

For debug purposes, SYNCARM (Register 0x03A[6]) can be

used to inform the user that alignment edges are being received

in continuous mode. Because the SYNCARM bit is self cleared

after an alignment edge is received, the user can arm the sync

(SYNCARM (Register 0x03A[6]) = 1), and then read back

SYNCARM. If SYNCARM = 0, the alignment edges are being

received and phase checks are occurring. Arming the sync

machine in this mode does not affect the operation of the

device.

One-Shot then Monitor Sync Mode (SYNCMODE = 0x9)

In one-shot then monitor mode, the user can monitor the phase

error in real time. Use this sync mode with a periodic SYSREF±

signal. A phase check and alignment occurs on the first alignment

edge received after the sync machine is armed. On all subsequent

alignment edges the phase is monitored and reported, but no clock

phase adjustment occurs.

The phase error can be monitored on the SYNC_CURRERR_L

occurs, CURRERR = 0 indicates that there is no difference

between the alignment edge and the LMFC edge. On every

subsequent alignment edge, the phase is checked. If the

alignment is lost, the phase error is reported in the SYNC_

CURRERR_L register in DAC clock cycles. If the phase error is

beyond the selected window tolerance (Register 0x034[2:0]),

one bit of Register 0x03D[7:6] is set high depending on whether

the phase error is on the low or high side.

When an alignment occurs, snapshots of the last phase error

(Register 0x03C[3:0]) and the corresponding error flags

(Register 0x03D[7:6]) are placed into readable registers for

reference (Register 0x038 and Register 0x039, respectively).

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