AD9144-EBZ datasheet(39/126 Pages) AD

39 / 126 page

AD9144

Data Sheet

Rev. A | Page 38 of 125

FREQUENCY (GHz)

5.0

7.5

2.5

AD9144 ALLOWED

CHANNEL LOSS

(LOW POWER MODE)

JESD204B SPEC ALLOWED

CHANNEL LOSS

EXAMPLE OF

JESD204B

COMPLIANT

CHANNEL

EXAMPLE OF

AD9144

COMPATIBLE

CHANNEL (LOW

POWER MODE)

EXAMPLE OF

AD9144

COMPATIBLE

CHANNEL

(NORMAL MODE)

AD9144 ALLOWED

CHANNEL LOSS

(NORMAL MODE)

Figure 39. Insertion Loss Allowed

–40

–35

–30

–25

–20

–15

–10

–5

0123456789

FREQUENCY (GHz)

STRIPLINE = 6”

STRIPLINE = 10”

STRIPLINE = 15”

STRIPLINE = 20”

STRIPLINE = 25”

STRIPLINE = 30”

Figure 40. Insertion Loss of 50 Ω Striplines on FR4

–40

–35

–30

–25

–20

–15

–10

–5

012

45678

FREQUENCY (GHz)

6” MICROSTRIP

10” MICROSTRIP

15” MICROSTRIP

20” MICROSTRIP

25” MICROSTRIP

30” MICROSTRIP

Figure 41. Insertion Loss of 50 Ω Microstrips on FR4

DATA LINK LAYER

The data link layer of the AD9144 JESD204B interface accepts

the deserialized data from the PHYs and deframes and descrambles

them so that data octets are presented to the transport layer to

be put into DAC samples. Figure 42 shows the link mode block

diagrams for single-link and dual-link configurations and the

interaction between the physical layer and logical layer. The

logical lanes and DACs can only be configured in sequential

order; for example in Mode 10, when in single-link mode, the

AD9144 only uses Logical Lane 0 and DAC0, and in dual-link

mode, only uses Logical Lane 0, Logical Lane 1 and DAC0,

DAC1. See the Mode Configuration Maps section for further

details on each of the mode configurations supported. The

architecture of the data link layer is shown in Figure 43. The

data link layer consists of a synchronization FIFO for each lane,

a crossbar switch, a deframer, and descrambler.

The AD9144 can operate as a single-link or dual-link high

speed JESD204B serial data interface. When operating in dual-

link mode, configure both links with the same JESD204B

parameters because they share a common device clock and system

reference. All eight lanes of the JESD204B interface handle link

layer communications such as code group synchronization,

frame alignment, and frame synchronization.

The AD9144 decodes 8-bit/10-bit control characters, allowing

marking of the start and end of the frame and alignment between

serial lanes. Each AD9144 serial interface link can issue a

synchronization request by setting its SYNCOUT0±/SYNCOUT1±

signal low. The synchronization protocol follows Section 4.9 of the

JESD204B standard. When a stream of four consecutive /K/

symbols is received, the AD9144 deactivates the synchronization

request by setting the SYNCOUT0±/SYNCOUT1± signal high

at the next internal LMFC rising edge. Then, it waits for the

transmitter to issue an ILAS. During the ILAS sequence, all

lanes are aligned using the /A/ to /R/ character transition as

described in the JESD204B Serial Link Establishment section.

Elastic buffers hold early arriving lane data until the alignment

character of the latest lane arrives. At this point, the buffers for

all lanes are released and all lanes are aligned (see Figure 44).

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