ADF4355-2 datasheet(10/38 Pages) AD

10 / 38 page

Data Sheet

ADF4355-2

Rev. B | Page 9 of 37

Pin No.

Mnemonic

Description

RSET

Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.

VREF

Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

VBIAS

Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.

25, 32

CREG1, CREG2

Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits. Nominal voltage

of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.

PDBRF

RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable.

DVDD

Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground

plane as close to this pin as possible.

REFINB

Complementary Reference Input. If unused, ac-couple this pin to AGND.

REFINA

Reference Input.

MUXOUT

Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the

scaled reference frequency to be externally accessible.

SDGND

Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.

Exposed Pad. The exposed pad must be connected to AGND.

ADF4355-2 bảng dữ liệu(PDF) 10 Page - Analog Devices