Data Sheet

ADuCM330/ADuCM331

Rev. C | Page 9 of 16

Parameter

Test Conditions/Comments

Min

Typ

Max

Typ

Unit

IDD ADC1 VADC

550

µA

IDD Internal Reference (1.2 V)

150

µA

IDD HFOSC

Reduction from 1% to 3% mode

50

µA

1

Not guaranteed by production test, but by design and/or characterization data at production release.

2

Valid for PGA current ADC gain settings of 4, 8, 16, 32, and 64.

3

System chopping enabled.

4

These specifications include temperature drift.

5

A user system calibration removes this error at a given temperature (and at a given gain for the current channel).

6

The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of

the temperature drift characterization data distribution.

7

Includes internal reference temperature drift.

8

The gain drift is included in the total gain error. This typical specification is an indicator of the gain error due to the temperature drift in the ADC. This typical value is

the mean of the temperature drift characterization data distribution.

9

Voltage channel specifications include resistive attenuator input stage, unless otherwise stated.

10

these input referred noise figures.

11

Valid after an initial self calibration.

12

It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach

can also be used to reduce the ADC input range (LSB size).

13

Valid for a differential input less than 10 mV.

14

The absolute value of the voltage of VTEMP and GND_SW must be 100 mV (minimum) for accurate operation of the temperature analog-to-digital converter (T-ADC).

15

Measured using box method.

16

The long-term stability specification is accelerated and noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.

17

Valid after an initial self gain calibration.

18

Die temperature.

19

Endurance is qualified to 10,000 cycles, as per JEDEC Standard 22 Method A117 and measured at −40°C, +25 °C, and +115°C. Typical endurance at +25°C is 100k cycles.

20

21

Measured with LIN communication active.

22

These specifications are not production tested but are supported by LIN compliance testing.

23

Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.

24

Typical additional supply current consumed during Flash/EE memory program and erase cycles is 3 mA and 1 mA, respectively.