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ICS9DB108 bảng dữ liệu(PDF) 3 Page - Integrated Circuit Systems

tên linh kiện ICS9DB108
Giải thích chi tiết về linh kiện  Eight Output Differential Buffer for PCI-Express
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ICS9DB108 bảng dữ liệu(HTML) 3 Page - Integrated Circuit Systems

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3
Integrated
Circuit
Systems, Inc.
ICS9DB108
0723D—01/08/04
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
GND
PWR
Ground pin.
26
PD#
IN
Asynchronous active low input pin used to power down the
device. The internal clocks are disabled and the VCO and the
crystal are stopped.
27
SRC_STOP#
IN
Active low input to stop diff outputs.
28
HIGH_BW#
PWR
3.3V input for selecting PLL Band Width
0 = High, 1= Low
29
DIF_4#
OUT
0.7V differential complement clock outputs
30
DIF_4
OUT
0.7V differential true clock outputs
31
VDD
PWR
Power supply, nominal 3.3V
32
GND
PWR
Ground pin.
33
DIF_5#
OUT
0.7V differential complement clock outputs
34
DIF_5
OUT
0.7V differential true clock outputs
35
OE_5
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
36
OE_6
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
37
DIF_6#
OUT
0.7V differential complement clock outputs
38
DIF_6
OUT
0.7V differential true clock outputs
39
VDD
PWR
Power supply, nominal 3.3V
40
GND
PWR
Ground pin.
41
DIF_7#
OUT
0.7V differential complement clock outputs
42
DIF_7
OUT
0.7V differential true clock outputs
43
OE_4
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44
OE_7
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
45
LOCK
OUT
3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
46
IREF
IN
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.



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