AD8421ARMZ-R7 datasheet(22/29 Pages) AD

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Data Sheet

AD8421

Rev. 0 | Page 21 of 28

REFERENCE TERMINAL

The output voltage of the AD8421 is developed with respect to

the potential on the reference terminal. This can be used to sense

the ground at the load, thereby taking advantage of the CMRR to

reject ground noise or to introduce a precise offset to the signal

at the output. For example, a voltage source can be tied to the REF

pin to level shift the output, allowing the AD8421 to drive a single-

supply ADC. The REF pin is protected with ESD diodes and

should not exceed either +VS or −VS by more than 0.3 V.

For best performance, maintain a source impedance to the

REF terminal that is below 1 Ω. As shown in Figure 61, the

reference terminal, REF, is at one end of a 10 kΩ resistor.

Additional impedance at the REF terminal adds to this 10 kΩ

resistor and results in amplification of the signal connected to

the positive input. The amplification from the additional RREF

can be calculated as follows:

2(10 kΩ + RREF)/(20 kΩ + RREF)

Only the positive signal path is amplified; the negative path is

unaffected. This uneven amplification degrades CMRR.

INCORRECT

CORRECT

AD8421

OP1177

–

REF

AD8421

REF

Figure 62. Driving the Reference Pin

INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8421 applies gain in the

first stage before removing the common-mode voltage in the

difference amplifier stage. Internal nodes between the first and

second stages (Node 1 and Node 2 in Figure 61) experience

a combination of a gained signal, a common-mode signal, and

a diode drop. The voltage supplies can limit the combined signal,

even when the individual input and output signals are not limited.

Figure 10 through Figure 13 show this limitation in detail.

LAYOUT

To ensure optimum performance of the AD8421 at the PCB level,

care must be taken in the design of the board layout. The pins of

the AD8421 are arranged in a logical manner to aid in this task.

–IN

+VS

VOUT

REF

–VS

+IN

TOP VIEW

(Not to Scale)

AD8421

Figure 63. Pin Configuration Diagram

Common-Mode Rejection Ratio over Frequency

Poor layout can cause some of the common-mode signals to

be converted to differential signals before reaching the in-amp.

Such conversions occur when one input path has a frequency

response that is different from the other. To maintain high CMRR

over frequency, closely match the input source impedance and

capacitance of each path. Place additional source resistance in

the input path (for example, input protection resistors) close to

the in-amp inputs, to minimize the interaction of the resistance

with parasitic capacitance from the PCB traces.

Parasitic capacitance at the gain setting pins (RG) can also affect

CMRR over frequency. If the board design has a component at

the gain setting pins (for example, a switch or jumper), choose

a component such that the parasitic capacitance is as small as

possible.

Power Supplies and Grounding

Use a stable dc voltage to power the instrumentation amplifier.

Noise on the supply pins can adversely affect performance.

Place a 0.1 μF capacitor as close as possible to each supply pin.

Because the length of the bypass capacitor leads is critical at

high frequency, surface-mount capacitors are recommended.

Any parasitic inductance in the bypass ground trace works against

the low impedance that is created by the bypass capacitor. As

shown in Figure 64, a 10 μF capacitor can be used farther away

from the device. For these larger value capacitors, which are

intended to be effective at lower frequencies, the current return

path distance is less critical. In most cases, the 10 μF capacitor

can be shared by other local precision integrated circuits.

AD8421

+VS

+IN

–IN

LOAD

REF

0.1µF

10µF

0.1µF

10µF

–VS

VOUT

Figure 64. Supply Decoupling, REF, and Output Referred to Local Ground

A ground plane layer helps to reduce parasitic inductances, which

minimizes voltage drops with changes in current. The area of

the current path is directly proportional to the magnitude of

parasitic inductances and, therefore, the impedance of the path

at high frequency. Large changes in currents in an inductive

decoupling path or ground return create unwanted effects due

to the coupling of such changes into the amplifier inputs.

Because load currents flow from the supplies, the load should be

connected at the same physical location as the bypass capacitor

grounds.

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