Philips Semiconductors

Product specification

NE/SE564

Phase-locked loop

1994 Aug 31

7

APPLICATIONS

FM Demodulator

The NE564 can be used as an FM demodulator. The connections

for operation at 5V and 12V are shown in Figures 7 and 8,

respectively. The input signal is AC coupled with the output signal

being extracted at Pin 14. Loop filtering is provided by the

capacitors at Pins 4 and 5 with additional filtering being provided by

the capacitor at Pin 14. Since the conversion gain of the VCO is not

very high, to obtain sufficient demodulated output signal the

frequency deviation in the input signal should be 1% or higher.

Modulation Techniques

The NE564 phase-locked loop can be modulated at either the loop

filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure

9. The approximate modulation frequency can be determined from

the frequency conversion gain curve shown in Figure 10. This curve

will be appropriate for signals injected into Pins 4 and 5 as shown in

Figure 9.

LOCK RANGE ADJUSTMENT

FM INPUT

BIAS

LOOP FILTER

ANALOG OUT

POST

FREQUENCY SET CAP

1k

1k

12V

80pF

1kHz

.01

µF

0.01

µF

0.1

µF

0.01

µF

0.47

µF

fO = 5MHz

fM = 1kHz

fO = 5MHz

6

7

3

1

810

9

12

13

14

15

5

4

11

2

16

.01

µF

200

564

DETECTION

FILTER

FILTER

SR01032

Figure 8. FM Demodulator at 12V

FSK Demodulation

The 564 PLL is particularly attractive for FSK demodulation since it

contains an internal voltage comparator and VCO which have TTL

compatible inputs and outputs, and it can operate from a single 5V

power supply. Demodulated DC voltages associated with the mark

and space frequencies are recovered with a single external

capacitor in a DC retriever without utilizing extensive filtering

networks. An internal comparator, acting as a Schmitt trigger with

an adjustable hysteresis, shapes the demodulated voltages into

compatible TTL output levels. The high-frequency design of the 564

enables it to demodulate FSK at high data rates in excess of 1.0M

baud.

Figure 10 shows a high-frequency FSK decoder designed for input

frequency deviations of +1.0MHz centered around a free-running

frequency of 10.8MHz. the value of the timing capacitance required

was estimated from Figure 8 to be approximately 40pF. A trimmer

MODULATING

FREQUENCY SET CAP

1k

2k

5V

5V

80pF

.01

µF

0.47

µF

fO = 5MHz

6

7

3

1

810

9

12

13

14

15

5

4

11

2

16

564

MODULATED OUTPUT

(TTL)

5V

FINE FREQUENCY

ADJUSTMENT

INPUT

1kHz

1kHz

1k

SR01033

Figure 9. Modulator

The lock range graph indicates that the +1.0MHz frequency

deviations will be within the lock range for input signal levels greater

than approximately 50mV with zero Pin 2 bias current. (While

strictly this figure is appropriate only for 50MHz, it can be used as a

The hysteresis was adjusted experimentally via the 10k

Ω

potentiometer and 2k

Ω bias arrangement to give the waveshape

shown in Figure 12 for 20k, 500k, 2M baud rates with square wave

FSK modulation. Note the magnitude and phase relationships of the

phase comparators’ output voltages with respect to each other and

to the FSK output. The high-frequency sum components of the input

and VCO frequency also are viable as noise on the phase

comparator’s outputs.

OUTLINE OF SETUP PROCEDURE

1. Determine operating frequency of the VCO: IF

loop, then

2. Calculate value of the VCO frequency set capacitor:

1

obtained, this value may be adjusted for best dynamic behavior,

V

I

B

2

.

4. Check VCO output frequency with digital counter at Pin 9 of

device (loop open, VCO to

adj. Pins 4 - 5 for exact center frequency, if needed.

5. Close loop and inject input signal to Pin 6. Monitor Pins 3 and 6

with two-channel scope. Lock should occur with