LPC18S50 datasheet(68/151 Pages) NXP

68 / 151 page

LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

68 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

• Random number generator (RNG) accessible through AES API.

• Unique ID for each device.

• Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI).

• Secure storage of encryption and decryption keys.

• Support for CMAC hash calculation to authenticate encrypted data.

• AES engine supports the following modes:

– Electronic Code Block (ECB) mode (encryption and decryption) with 128-bit key.

– Cypher Block Chaining (CBC) mode (encryption and decryption) with 128-bit key.

• The AES engine is compliant with the FIPS (Federal Information Processing

Standard) Publication 197, Advanced Encryption Standard (AES).

• Random Number Generator (RNG) is supported by the AES API and passes the

following tests:

– diehard

– FIPS_140-1

– NIST

• Data is processed in little endian mode. This means that the first byte read from flash

is integrated into the AES codeword as least significant byte. The 16th byte read from

flash is the most significant byte of the first AES codeword.

• AES peak engine performance of 0.5 byte/clock cycle.

• DMA transfers supported through the GPDMA.

7.13.2 State Configurable Timer (SCTimer/PWM) subsystem

The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input

capture operations. The inputs and outputs of the SCTimer/PWM are shared with the

capture and match inputs/outputs of the 32-bit general-purpose counter/timers.

The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

• State variable

• Limit, halt, stop, and start conditions

• Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the

SCTimer/PWM, but the last three can use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

7.13.2.1

Features

• Two 16-bit counters or one 32-bit counter.

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