2006-01-23

4

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Write Cycle Timing Diagram (Input pulse levels –0.6 V to 2.4 V)

Read Cycle Timing Diagram

Switching Specifications

(over operating temperature range and V

Symbol

Description

Min.

Units Symbol

Description

Min.

Units

T

acc

Display Access Time—Write

210

ns

T

dh

Data Write Time

20

ns

T

acc

Display Access Time—Read

230

ns

T

r

Chip Enable Active Prior to Valid Data

160

ns

T

acs

Address Setup Time to CE

10

ns

T

rd

Read Active Prior to Valid Data

95

µs

T

ce

Chip Enable Active Time—Write

140

ns

T

df

Read Data Float Delay

10

ns

T

ce

Chip Enable Active Time—Read

160

ns

T

rc

Reset Active Time

300

ns

T

ach

Address Hold Time to CE

20

ns

T

w

Write Active Time

100

ns

T

ces

Chip Enable Active Prior to

Rising Edge—Write

140

ns

T

wd

Data Valid Prior to

Rising Edge of Write Signal

50

ns

T

ces

Chip Enable Active Prior to

Rising Edge—Read

160

ns

T

ceh

Chip Enable Hold to Rising Edge of

Read/Write Signal

0

ns

T

cer

Chip Enable Recovery Time

60

ns

Tacc

Twd

Tdh

Tw

Tces

Tcer

Tceh

Tacs

Tach

Tacs

A0-A3

FL

Tce

CE

WR

D0-D7

Input pulse levels —0.6 V to 2.4 v

Tacc

Trd

Tdf

Tr

Tces

Tcer

Tceh

Tacs

Tach

Tacs

A0-A3

FL

Tce

CE

RD

D0-D7