TCS34721 datasheet(24/40 Pages) AMSCO

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[v1-02] 2016-Feb-08

TCS3472 − Register Description

RGBC Interrupt Threshold Registers

(0x04 − 0x07)

The RGBC interrupt threshold registers provides the values to

be used as the high and low trigger points for the comparison

function for interrupt generation. If the value generated by the

clear channel crosses below the lower threshold specified, or

above the higher threshold, an interrupt is asserted on the

interrupt pin.

Figure 29:

RGBC Interrupt Threshold Registers

Persistence Register (0x0C)

The persistence register controls the filtering interrupt

capabilities of the device. Configurable filtering is provided to

allow interrupts to be generated after each integration cycle or

if the integration has produced a result that is outside of the

values specified by the threshold register for some specified

amount of time.

Figure 30:

Persistence Register

Address

Bits

Description

AILTL

0x04

7:0

RGBC clear channel low threshold lower byte

AILTH

0x05

7:0

RGBC clear channel low threshold upper byte

AIHTL

0x06

7:0

RGBC clear channel high threshold lower byte

AIHTH

0x07

7:0

RGBC clear channel high threshold upper byte

543

Reserved

APERS

Field

Bits

Description

PPERS

7:4

Reserved

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