TCS34721 datasheet(22/40 Pages) AMSCO

22 / 40 page

Page 22

ams Datasheet

Document Feedback

[v1-02] 2016-Feb-08

TCS3472 − Register Description

Enable Register (0x00)

The ENABLE register is used primarily to power the TCS3472

device ON and OFF, and enable functions and interrupts as

shown below.

Figure 26:

Enable Register

Notes:

1. See Power Management section for more information.

2. A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated.

321

Reserved

AIEN

WEN

Reserved

AEN

PON

Fields

Bits

Description

Reserved

7:5

Reserved. Write as 0.

AIEN

RGBC interrupt enable. When asserted, permits RGBC interrupts to be

generated.

WEN

Wait enable. This bit activates the wait feature. Writing a 1 activates the wait

timer. Writing a 0 disables the wait timer.

Reserved

Reserved. Write as 0.

AEN

RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates the

RGBC. Writing a 0 disables the RGBC.

PON(1), (2)

Power ON. This bit activates the internal oscillator to permit the timers and

ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0

disables the oscillator.

TCS34721 bảng dữ liệu(PDF) 22 Page - ams AG

TCS34721 bảng dữ liệu(HTML) 22 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

bảng dữ liệu tải về

Link URL