AD9363ABCZ datasheet(5/32 Pages) AD

5 / 32 page

Data Sheet

AD9363

Rev. D | Page 5 of 32

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Third-Order Output Intermodulation

Intercept Point

OIP3

dBm

Carrier Leakage

−50

dBc

0 dB attenuation

−31

dBc

40 dB attenuation

Noise Floor

−154

dBm/Hz

90 MHz offset

Isolation

TX1 to TX2

TX2 to TX1

1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin

names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

Table 2.

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

TX MONITOR INPUTS

(TX_MON1, TX_MON2)

Maximum Input Level

dBm

Dynamic Range

Accuracy

LO SYNTHESIZER

LO Frequency Step

2.4

2.4 GHz, 40 MHz reference clock

Integrated Phase Noise

0.3

°rms

100 Hz to 100 MHz

REFERENCE CLOCK (REF_CLK)

REF_CLK is the input to the

XTALN pin

Input Frequency Range

MHz

External oscillator

Input Signal Level

1.3

V p-p

AC-coupled external oscillator

AUXILIARY ADC

Resolution

Bits

Input Voltage

Minimum

0.05

Maximum

VDDA1P3_BB −

0.05

AUXILIARY DAC

Resolution

Bits

Output Voltage

Minimum

0.5

Maximum

VDD_GPO − 0.3

Output Current

DIGITAL SPECIFICATIONS

(CMOS)

Logic Inputs

Input Voltage High

VDD_INTERFACE ×

0.8

VDD_INTERFACE

Input Voltage Low

VDD_INTERFACE ×

0.2

Input Current High

−10

+10

μA

Input Current Low

−10

+10

μA

Logic Outputs

Output Voltage High

VDD_INTERFACE ×

0.8

VDD_INTERFACE

Output Voltage Low

VDD_INTERFACE ×

0.2

DIGITAL SPECIFICATIONS (LVDS)

Logic Inputs

Input Voltage Range

825

1575

Each differential input in the

pair

Input Differential Voltage

Threshold

−100

+100

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