AD7616

Data Sheet

Rev. 0 | Page 42 of 50

CONFIGURATION REGISTER

The configuration register is used in software mode to configure many of the main functions of the ADC, including the sequencer, burst

mode, oversampling, and CRC options.

Address: 0x02, Reset: 0x0000, Name: Configuration Register

Table 21. Bit Descriptions for the Configuration Register

Bits

Bit Name

Settings

Description

Access

[15:9]

Addressing

0

Bits[15:9] define the address of the relevant register. See the Addressing Registers

section for further details.

0x0

RW

8

RESERVED

Reserved.

0x0

R/W

7

SDEF

Self detector error flag.

N/A

R

0

Test passed. The AD7616 has configured itself successfully after power-up.

1

Test failed. An issue was detected during device configuration. A reset is required.

6

BURSTEN

Burst mode enable.

0x0

RW

0

Burst mode is disabled. Each channel pair to be converted requires a CNVST pulse.

1

A single CNVST pulse converts every channel pair programmed in the 32-layer

sequencer stack registers up to and including the layer defined by the SSRENx bit. See

the Software Mode Sequencer section and the Software Mode Burst section for

further details.

5

SEQEN

Channel sequencer enable.

0x0

RW

0

The channel sequencer is disabled.

1

The channel sequencer is enabled.

[4:2]

OS

Oversampling (OS) ratio, samples per channel.

0x0

RW

000

Oversampling disabled.

001

Oversampling enabled, OSR = 2.

010

Oversampling enabled, OSR = 4.

011

Oversampling enabled, OSR = 8.

100

Oversampling enabled, OSR = 16.

101

Oversampling enabled, OSR = 32.

110

Oversampling enabled, OSR = 64.

111

Oversampling enabled, OSR = 128.

1

STATUSEN

Status register output enable.

0x0

RW

0

The status register is not read out when reading the conversion result.

1

The status register is read out at the end of all the conversion words (including the

self test channel if enabled in sequencer mode) if all the selected channels are read

out. The CRC result is included in the last eight bits.

0

CRCEN

CRC enable. The STATUSEN and CRCEN bits have identical functionality.

0x0

RW

CRC Enable

Status Regis ter Output Enable

Self-Detector Error flag

OS ratio s am ples per channel

111: OS128.

110: OS64.

101: OS32.

100: OS16.

011: OS8.

010: OS4.

001: OS2.

000: OS1.

Burs t Mode enable

Channel Sequencer Enable

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

0

11

0

12

0

13

0

14

0

15

0

[15:9] Addressing (R/W)

[0] CRCEN (R/W)

[8] RESERVED

[1] STATUSEN (R/W)

[7] SDEF (R)

[4:2] OS (R/W)

[6] BURSTEN (R/W)

[5] SEQEN (R/W)