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WM8756 bảng dữ liệu(PDF) 14 Page - Wolfson Microelectronics plc

tên linh kiện WM8756
Giải thích chi tiết về linh kiện  192KHZ SIX CHANNEL SACD COMPATIBLE AUDIO DAC
PDF  39 Pages
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nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
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WM8756 bảng dữ liệu(HTML) 14 Page - Wolfson Microelectronics plc

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WM8756
Advance Information
AI Rev 1.3 October 2001
14
minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above
requirements are met. The WM8756 will automatically detect when data with a LRCIN period of exactly 32
is sent, and select 16 bit mode - overriding any previously programmed word length. Word length will
revert to the previously programmed value if a LRCIN period other than 32 is detected.
In DSP early or DSP late mode, all 6 channels are time multiplexed onto DIN0. LRCIN is used as a frame
sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 6
times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising edge
is correctly positioned (see Figures 9 and 10).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN transition.
LRCIN is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN0/1/2
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 6 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition.
LRCIN is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN0/1/2
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 7 Right Justified Mode Timing Diagram



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