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WM8281ECS/R bảng dữ liệu(PDF) 274 Page - Cirrus Logic |
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WM8281ECS/R bảng dữ liệu(HTML) 274 Page - Cirrus Logic |
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274 / 392 page  WM8281 274 Rev 4.0 BCLK AND LRCLK CONTROL The digital audio interfaces (AIF1, AIF2 and AIF3) use BCLK and LRCLK signals for synchronisation. In master mode, these are output signals, generated by the WM8281. In slave mode, these are input signals to the WM8281. It is also possible to support mixed master/slave operation. The BCLK and LRCLK signals are controlled as illustrated in Figure 70 . See the “Digital Audio Interface Control ” section for further details of the relevant control registers. Note that the BCLK and LRCLK signals are synchronised to SYSCLK or ASYNCLK, depending upon the applicable clocking domain for the respective interface. See “Digital Core” for further details. AIF1_BCLK_FREQ [4:0] f/N AIF1BCLK AIF1LRCLK AIF1RX_BCPF [12:0] f/N GPIO1 (AIF1TXLRCLK) AIF1TX_BCPF [12:0] SYSCLK MASTER MODE CLOCK OUTPUTS f/N AIF1_BCLK_MSTR AIF1RX_LRCLK_MSTR AIF1TX_LRCLK_MSTR AIF2_BCLK_FREQ [4:0] f/N AIF2BCLK AIF2LRCLK AIF2RX_BCPF [12:0] f/N GPIO2 (AIF2TXLRCLK) AIF2TX_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF2_BCLK_MSTR AIF2RX_LRCLK_MSTR AIF2TX_LRCLK_MSTR AIF3_BCLK_FREQ [4:0] f/N AIF3BCLK AIF3LRCLK AIF3RX_BCPF [12:0] f/N GPIO3 (AIF3TXLRCLK) AIF3TX_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF3_BCLK_MSTR AIF3RX_LRCLK_MSTR AIF3TX_LRCLK_MSTR ASYNCCLK The clock reference for each AIF is SYSCLK or ASYNCCLK AIFn is clocked from SYSCLK if AIFn_RATE < 1000 AIFn is clocked from ASYNCCLK if AIFn_RATE >= 1000 (see note below) (see note below) (see note below) Figure 70 BCLK and LRCLK Control CONTROL INTERFACE CLOCKING Register map access is possible with or without a system clock. Clocking is provided from SYSCLK, when available; the SYSCLK_SRC register selects the applicable SYSCLK source. See “Control Interface” for further details of control register access. |
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