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WM8281ECS/R bảng dữ liệu(PDF) 222 Page - Cirrus Logic |
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WM8281ECS/R bảng dữ liệu(HTML) 222 Page - Cirrus Logic |
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222 / 392 page  WM8281 222 Rev 4.0 REGISTER ADDRESS LABEL REFERENCE GP5_FALL_TRIG_STS GP5_RISE_TRIG_STS JD1_FALL_TRIG_STS JD1_RISE_TRIG_STS 0D51h MICD_CLAMP_FALL_EINT1 See “Interrupts” MICD_CLAMP_RISE_EINT1 GP5_FALL_EINT1 GP5_RISE_EINT1 JD1_FALL_EINT1 JD1_RISE_EINT1 0D52h MICD_CLAMP_FALL_EINT2 See “Interrupts” MICD_CLAMP_RISE_EINT2 GP5_FALL_EINT2 GP5_RISE_EINT2 JD1_FALL_EINT2 JD1_RISE_EINT2 0D53h IM_MICD_CLAMP_FALL_EINT1 See “Interrupts” IM_MICD_CLAMP_RISE_EINT1 IM_GP5_FALL_EINT1 IM_GP5_RISE_EINT1 IM_JD1_FALL_EINT1 IM_JD1_RISE_EINT1 0D54h IM_MICD_CLAMP_FALL_EINT2 See “Interrupts” IM_MICD_CLAMP_RISE_EINT2 IM_GP5_FALL_EINT2 IM_GP5_RISE_EINT2 IM_JD1_FALL_EINT2 IM_JD1_RISE_EINT2 0D56h MICD_CLAMP_DB See “External Accessory Detection” JD1_DB 3000h to 31FFh WSEQ_DATA_WIDTHn See “Control Write Sequencer” WSEQ_ADDRn WSEQ_DELAYn WSEQ_DATA_STARTn WSEQ_DATAn Table 81 Sleep Mode ‘Always-On’ Control Registers The ‘Always-On’ digital input / output pins are listed in Table 82. All other digital input pins will have no effect in Sleep mode. The IRQ ¯¯¯ output is normally de-asserted in Sleep mode. Note that, in Sleep mode, the IRQ ¯¯¯ output can only be asserted in response to the JD1 or GP5 control signals (these described in the following section). If the IRQ ¯¯¯ output is asserted in Sleep mode, it can only be de-asserted after a Wake-Up transition. PIN NAME DESCRIPTION REFERENCE LDOENA Enable pin for LDO1 See “Charge Pumps, Regulators and Voltage Reference ” RESET ¯¯¯¯¯¯ Digital Reset input (active low) See “Hardware Reset, Software Reset, Wake-Up, and Device ID ” MCLK2 Master clock 2 See “Clocking and Sample Rates” GPIO5 General Purpose pin GPIO5 See “General Purpose Input / Output” IRQ ¯¯¯ Interrupt Request (IRQ) output See “Interrupts” Table 82 Sleep Mode ‘Always-On’ Digital Input Pins |
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