Integrated

Circuit

Systems, Inc.

ICS950905

Advance Information

Block Diagram

950905 Rev - 11/26/01

Pin Configuration

Recommended Application:

VIA P4X266 chipset with PC133 or DDR memory.

Output Features:

•

2 - Pair of differential CPU clocks @ 3.3V

•

1 - Pair of differential push pull CPU_CS clocks @ 2.5V

•

3 - AGP @ 3.3V

•

9 - PCI @ 3.3V

•

1- IOAPIC @ 2.5V

•

1 - 48MHz @ 3.3V fixed

•

1 - 24_48MHz @ 3.3V

•

1 - REF @ 3.3V, 14.318MHz

Features/Benefits:

•

Programmable output frequency.

•

Programmable output divider ratios.

•

Programmable output rise/fall time.

•

Programmable output skew.

•

Programmable spread percentage for EMI control.

•

Watchdog timer technology to reset system

if system malfunctions.

•

Programmable watch dog safe frequency.

•

Support I

operations.

•

For DDR and or PC133 SDRAM system use ICS93718

as the memory buffer.

•

Uses external 14.318MHz crystal.

Key Specifications:

•

CPU_CS - CPU0: <±250ps

•

CPU_CS - AGP: <±250ps

•

PCI - PCI: <500ps

•

CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns

Programmable Timing Control Hub™ for P4™

1. These outputs have 2X drive strength.

* These inputs have a internal Pull-up resistor

of 120K to VDD

** These inputs have a internal pull-down to GND

48-Pin 300-mil SSOP

Frequency Table

I REF

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

IOAPIC

PCICLK (7:0)

AGPCLK (2:0)

RESET#

PCICLK_F

3

X1

X2

XTAL

OSC

CPU

DIVDER

CPU

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

AGP

DIVDER

Stop

Stop

Stop

SEL24_48

SDATA

SCLK

FS (3:0)

PD#

PCI_STOP#

CPU_STOP#

MULTI_SEL

Vtt_PWRGD#

Control

Logic

Config.

Reg.

/ 2

REF0

CPUCLKT_(1:0)

CPUCLKC_(1:0)

CPUCLK_PPT

CPUCLK_PPC

WDEN

WDTB

0

L

E

S

I

T

L

U

M

t

e

g

r

a

T

d

r

a

o

B

Z

m

r

e

T

/

e

c

a

r

T

,

R

e

c

n

e

r

e

f

e

R

=

f

e

r

I

V

D

D

)

r

R

*

3

(

/

t

u

p

t

u

O

t

n

e

r

r

u

C

Z

@

h

o

V

0s

m

h

o

0

5

,

%

1

1

2

2

=

r

R

A

m

0

0

.

5

=

f

e

r

I

F

E

R

I

*

4

=

h

o

I0

5

@

V

0

.

1

1s

m

h

o

0

5

,

%

1

5

7

4

=

r

R

A

m

2

3

.

2

=

f

e

r

I

F

E

R

I

*

6

=

h

o

I0

5

@

V

7

.

0

3

S

F2

S

F1

S

F0

S

F

K

L

C

U

P

C

z

H

M

P

G

A

z

H

M

K

L

C

I

C

P

z

H

M

00

0

0

0

0

.

0

6

10

0

.

0

80

0

.

0

4

00

0

1

0

0

.

4

6

10

0

.

2

80

0

.

1

4

001

0

0

6

.

6

6

10

6

.

6

60

3

.

3

3

001

1

0

0

.

0

7

10

0

.

8

60

0

.

4

3

01

0

0

0

0

.

5

7

10

0

.

0

70

0

.

5

3

01

0

1

0

0

.

0

8

10

0

.

2

70

0

.

6

3

01

1

0

0

0

.

5

8

10

0

.

4

70

0

.

7

3

01

1

1

0

0

.

0

9

10

0

.

6

70

0

.

8

3

100

0

0

8

.

6

60

8

.

6

60

4

.

3

3

100

1

0

9

.

0

0

17

2

.

7

63

6

.

3

3

10

1

0

0

6

.

3

3

10

8

.

6

60

4

.

3

3

10

1

1

0

4

.

0

0

20

8

.

6

60

4

.

3

3

11

0

0

0

6

.

6

60

6

.

6

60

3

.

2

3

11

0

1

0

0

.

0

0

10

6

.

6

60

3

.

3

3

11

1

0

0

0

.

0

0

20

6

.

8

60

3

.

3

3

11

1

1

0

3

.

3

3

10

6

.

8

60

3

.

3

3

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

VDDREF

GND

X1

X2

VDD48

*FS3/48MHz

*FS2/24_48MHz

GND

*FS0/PCICLK_F

**FS1/PCICLK0

*MULTI_SEL/PCICLK1

GND

PCICLK2

PCICLK3

VDDPCI

PCICLK4

PCICLK5

PCICLK6

GND

PCICLK7

*PD#

AGPCLK0

VDDAGP

*WDTB/

**WDEN/

VDDLAPIC

GND

N/C

IOAPIC

GND

VDDCPU_PP (2.5V)

CPUCLK_PPT

CPUCLK_PPC

CPUCLKT_0

CPUCLKC_0

VDDCPU (3.3V)

I REF

GND

CPUCLKT_1

CPUCLKC_1

Vtt_PWRGD#

CPU_STOP#*

PCI_STOP#*

RESET#

SDATA

SCLK

AGPCLK2

AGPCLK1

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25