HT46R23 datasheet(14/42 Pages) HOLTEK

14 / 42 page

HT46R23

Rev. 1.30

August 17, 2001

WDT Time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Rese

(HALT)

WDT Time-out

(HALT)*

ADRL

xx-- ----

uu-- ----

ADRH

xxxx xxxx

uuuu uuuu

ADCR

0100 0000

uuuu uuuu

ACSR

1--- --00

--- --00

u--- --uu

Note: ²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

A timer/event counter (TMR) is implemented in the

microcontroller. The timer/event counter contains an

16-bit programmable count-up counter and the clock may

come from an external source or the system clock.

Using the internal system clock, there is only one refer-

ence time-base. The internal clock source comes from

fSYS. The external clock input allows the user to count

external events, measure time intervals or pulse widths,

or to generate an accurate time base.

There are three registers related to the timer/event coun-

ter; TMRH (0CH), TMRL (0DH), TMRC (0EH). Writing

TMRL will only put the written data to an internal

lower-order byte buffer (8 bits) and writing TMRH will

transfer the specified data and the contents of the

lower-order byte buffer to TMRH and TMRL preload regis-

ters, respectively. The timer/event counter preload register

is changed by each writing TMRH operations. Reading

TMRH will latch the contents of TMRH and TMRL coun-

ters to the destination and the lower-order byte buffer, re-

spectively. Reading the TMRL will read the contents of the

lower-order byte buffer. The TMRC is the timer/event

counter control register, which defines the operating

mode, counting enable or disable and active edge.

The TM0, TM1 bits define the operating mode. The event

count mode is used to count external events, which means

the clock source comes from an external (TMR) pin. The

timer mode functions as a normal timer with the clock

source coming from the fINT clock. The pulse width mea-

surement mode can be used to count the high or low level

duration of the external signal (TMR). The counting is based

on the fINT.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current con-

tents in the timer/event counter to FFFFH. Once overflow

occurs, the counter is reloaded from the timer/event coun-

ter preload register and generates the interrupt request

flag (TF; bit 5 of INTC0) at the same time.

In the pulse width measurement mode with the TON

and TE bits equal to one, once the TMR has received a

transient from low to high (or high to low if the TE bits is

²0²) it will start counting until the TMR returns to the orig-

inal level and resets the TON. The measured result will

remain in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON will be cleared au-

tomatically after the measurement cycle is completed.

TM 1

TM 0

TM R

TM 1

TM 0

TO N

P u l s e W i dt h

M eas ur e m ent

M ode C ont r o l

T i m e r / E v ent C ount er

P r el oad R e gi s t er

T i m e r / E v ent

C ount e r

Da t a B u s

R e l oad

O v er f l ow

t o I nt er r upt

1/ 2

PF D

8- s t age p r e s cal er

8- 1 M U X

f SY S

f IN T

PS C 2 ~ P SC 0

( 6 + 2 ) or ( 7+ 1)

com pa r e

PW M

T o P D 0 /P D 1 ci r cu i t

Timer/Event Counter

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