HD64F3687 datasheet(21/504 Pages) RENESAS

21 / 504 page

Rev. 3.00, 05/03, page xxi of xxx

Figure 12.11 Contention between TCNTV Write and Clear ......................................................167

Figure 12.12 Contention between TCORA Write and Compare Match .....................................168

Figure 12.13 Internal Clock Switching and TCNTV Operation .................................................168

Section 13 Timer Z

Figure 13.1 Timer Z Block Diagram ..........................................................................................171

Figure 13.2 Timer Z (Channel 0) Block Diagram.......................................................................172

Figure 13.3 Timer Z (Channel 1) Block Diagram.......................................................................173

Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode and

Complementary PWM Mode ...................................................................................179

Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) ........189

Figure 13.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits)).............190

Figure 13.7 Example of Counter Operation Setting Procedure ..................................................191

Figure 13.8 Free-Running Counter Operation ............................................................................192

Figure 13.9 Periodic Counter Operation .....................................................................................193

Figure 13.10 Count Timing at Internal Clock Operation ............................................................193

Figure 13.11 Count Timing at External Clock Operation (Both Edges Detected)......................194

Figure 13.12 Example of Setting Procedure for Waveform Output by Compare Match ............194

Figure 13.13 Example of 0 Output/1 Output Operation..............................................................195

Figure 13.14 Example of Toggle Output Operation ...................................................................196

Figure 13.15 Output Compare Timing........................................................................................196

Figure 13.16 Example of Input Capture Operation Setting Procedure .......................................197

Figure 13.17 Example of Input Capture Operation.....................................................................198

Figure 13.18 Input Capture Signal Timing .................................................................................198

Figure 13.19 Example of Synchronous Operation Setting Procedure.........................................199

Figure 13.20 Example of Synchronous Operation ......................................................................200

Figure 13.21 Example of PWM Mode Setting Procedure ..........................................................201

Figure 13.22 Example of PWM Mode Operation (1) .................................................................202

Figure 13.23 Example of PWM Mode Operation (2) .................................................................203

Figure 13.24 Example of PWM Mode Operation (3) .................................................................204

Figure 13.25 Example of PWM Mode Operation (4) .................................................................205

Figure 13.26 Example of Reset Synchronous PWM Mode Setting Procedure ...........................207

Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ......208

Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ......209

Figure 13.29 Example of Complementary PWM Mode Setting Procedure................................211

Figure 13.30 Canceling Procedure of Complementary PWM Mode ..........................................212

Figure 13.31 Example of Complementary PWM Mode Operation (1).......................................213

Figure 13.32 Example of Complementary PWM Mode Operation (2).......................................214

Figure 13.33 Timing of Overshooting ........................................................................................215

Figure 13.34 Timing of Undershooting ......................................................................................215

Figure 13.35 Compare Match Buffer Operation .........................................................................216

Figure 13.36 Input Capture Buffer Operation.............................................................................217

Figure 13.37 Example of Buffer Operation Setting Procedure ...................................................217

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