HD64F3687 datasheet(77/504 Pages) RENESAS

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77 / 504 page

Rev. 3.00, 05/03, page 47 of 472

Section 3 Exception Handling

Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.

• Reset

A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared

by the

RES pin. The chip is also reset when the watchdog timer overflows, and exception handling

starts. Exception handling is the same as exception handling by the

RES pin.

• Trap Instruction

Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction

generates a vector address corresponding to a vector number from 0 to 3, as specified in the

instruction code. Exception handling can be executed at all times in the program execution state,

regardless of the setting of the I bit in CCR.

• Interrupts

External interrupts other than NMI and internal interrupts other than address break are masked by

the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the

current instruction or exception handling ends, if an interrupt request has been issued.

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