IDT72V3653_16 datasheet(1/30 Pages) IDT

tên linh kiện	IDT72V3653

Giải thích chi tiết về linh kiện	3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING

PDF	30 Pages

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nhà sản xuất	IDT [Integrated Device Technology]

Trang chủ	http://www.idt.com

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1 / 30 page

1

MAY 2016

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING

2,048 x 36

4,096 x 36

8,192 x 36

IDT72V3653

IDT72V3663

IDT72V3673

DSC-4662/5

COMMERCIAL TEMPERATURE RANGE

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO

™ isatrademarkofIntegratedDeviceTechnology,Inc.

FEATURES

••••• Memory storage capacity:

IDT72V3653

–

2,048 x 36

IDT72V3663

–

4,096 x 36

IDT72V3673

–

8,192 x 36

••••• Clock frequencies up to 100 MHz (6.5 ns access time)

••••• Clocked FIFO buffering data from Port A to Port B

••••• IDT Standard timing (using EF and FF) or First Word Fall

Through Timing (using OR and IR flag functions)

••••• Programmable Almost-Empty and Almost-Full flags; each has

five default offsets (8, 16, 64, 256 and 1,024)

••••• Serial or parallel programming of partial flags

••••• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

••••• Big- or Little-Endian format for word and byte bus sizes

••••• Retransmit Capability

••••• Reset clears data and configures FIFO, Partial Reset clears data

but retains configuration settings

••••• Mailbox bypass registers for each FIFO

••••• Free-running CLKA and CLKB may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

••••• Easily expandable in width and depth

••••• Auto power down minimizes power dissipation

••••• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

••••• Pin and functionally compatible versions of the 5V operating

IDT723653/723663/723673

••••• Pin compatible with the lower density parts, IDT72V3623/

72V3633/72V3643

••••• Industrial temperature range (–40

°°°°°C to +85°°°°°C) is available

••••• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

Mail 1

Register

Programmable Flag

Offset Registers

Status Flag

Logic

EF/OR

AE

36

FF/IR

AF

36

Timing

Mode

FWFT

A0-A35

FS2

FS0/SD

FS1/

SEN

B0-B35

Write

Pointer

Read

Pointer

Mail 2

Register

MBF2

CLKB

CSB

W/RB

ENB

MBB

BE

BM

SIZE

Port-B

Control

Logic

13

4662 drw01

RAM ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

CLKA

CSA

W/

RA

ENA

MBA

Port-A

Control

Logic

FIFO1

Mail1,

Mail2,

Reset

Logic

RS1

MBF1

36

PRS

36

RS2

36

FIFO

Retransmit

Logic

RT

RTM

Số phần tương tự - IDT72V3653_16

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