28

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

Figure 21. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with

Programmable Flags used in Depth Expansion Configuration

NOTES:

1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)

2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.

3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the

4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:

DATA IN (Dn)

READ CLOCK (CLKB)

READ ENABLE (ENB)

EMPTY FLAG/

OUTPUT READY (

EF/OR)

CHIP SELECT (

CSB)

DATA OUT (Qn)

TRANSFER CLOCK

4662 drw23

IDT

72V3653

72V3663

72V3673

IDT

72V3653

72V3663

72V3673

WRITE

READ

MBA

CHIP SELECT (

CSA)

WRITE SELECT (W/

RA)

WRITE ENABLE (ENA)

ALMOST-FULL FLAG (

AF)

FULL FLAG/

INPUT READY (

FF/IR)

WRITE CLOCK (CLKA)

CLKB

EF/OR

ENB

CSB

W/RB

MBB

CLKA

ENA

FF/IR

CSA

MBA

W/

RA

READ SELECT (

W/RB)

ALMOST-EMPTY FLAG (

AE)

MBB

n

n

n

Qn

Dn