MCP37231 datasheet(89/144 Pages) MICROCHIP

89 / 144 page

MCP37231/21-200 AND MCP37D31/21-200

DS20005322D-page 89

 2014-2016 Microchip Technology Inc.

ADDRESS 0X53 – CLOCK SOURCE SELECTION

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

FCB<6:4>

CLK_SOURCE

FCB<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

FCB<6:4>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

bit 4

CLK_SOURCE: Select internal timing source

PLL output is selected as timing source

External clock input is selected as timing source (Default)

bit 3-0

FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

ADDRESS 0X54 – PLL REFERENCE DIVIDER

R/W-0

PLL_REFDIV<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

PLL_REFDIV<7:0>: PLL Reference clock divider control bits(1)

1111-1111

= PLL reference divided by 255 (if PLL_REFDIV<9:8> = 00)

1111-1110

= PLL reference divided by 254 (if PLL_REFDIV<9:8> = 00)

• • •

0000-0011

= PLL reference divided by 3 (if PLL_REFDIV<9:8> = 00)

0000-0010

= Do not use (No effect)

0000-0001

= PLL reference divided by 1 (if PLL_REFDIV<9:8> = 00)

0000-0000

= PLL reference not divided (if PLL_REFDIV<9:8> = 00) (Default)

Note

PLL_REFDIV is a 10-bit wide setting. See Address 0x55 (Register 5-10) for the upper two bits and Table 5-4 for PLL_REF-

DIV<9:0> bit settings. This setting controls the clock division ratio of the PLL reference clock (external clock input at the CLK

pin) before the PLL phase-frequency detector circuitry. Note that the divider value of 2 is not supported. EN_PLL_REFDIV in

Address 0x59 (Register 5-14) must be set.

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