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LAN89730 bảng dữ liệu(PDF) 18 Page - Microchip Technology

tên linh kiện LAN89730
Giải thích chi tiết về linh kiện  Implements Reduced Power Operating Modes
PDF  218 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
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LAN89730
DS60001348A-page 18
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TABLE 2-3:
JTAG PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1JTAG Test
Port Reset
(Internal PHY
Mode)
nTRST
IS
(PU)
In Internal PHY Mode, this active-low pin func-
tions as the JTAG test port reset input.
Receive Data
0
(External
PHY Mode)
RXD0
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 0 input from the external PHY.
1JTAG Test
Data Out
(Internal PHY
Mode)
TDO
O8
In Internal PHY Mode, this pin functions as the
JTAG data output.
PHY Reset
(External
PHY Mode)
nPHY_RST
O8
In External PHY Mode, this active-low pin func-
tions as the PHY reset output.
1JTAG Test
Clock
(Internal PHY
Mode)
TCK
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG test clock. The maximum operating fre-
quency of this clock is 25 MHz.
Receive Data
1
(External
PHY Mode)
RXD1
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 1 input from the external PHY.
1JTAG Test
Mode Select
(Internal PHY
Mode)
TMS
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG test mode select.
Receive Data
2
(External
PHY Mode)
RXD2
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 2 input from the external PHY.
1JTAG Test
Data Input
(Internal PHY
Mode)
TDI
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG data input.
Receive Data
3
(External
PHY Mode)
RXD3
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 3 input from the external PHY.



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