LAN89730 datasheet(67/218 Pages) MICROCHIP

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DS60001348A-page 67

LAN89730

Filter x Mask 1 corresponds to bits [63:32]. Where the lsb corresponds to the first byte on the wire.

Filter x Mask 2 corresponds to bits [95:64]. Where the lsb corresponds to the first byte on the wire.

Filter x Mask 3 corresponds to bits [127:96]. Where the lsb corresponds to the first byte on the wire.

The following tables define the WUFF register structures.

The Filter i command register controls Filter i operation. Table 4-49 shows the Filter i command register.

The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined

by Filter i. Table 4-50 describes the Filter i Offset bit fields.

TABLE 4-48:

FILTER I BYTE MASK BIT DEFINITIONS

Filter i Byte Mask Description

Bits

Description

127:0

Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte pattern-offset + j of the

incoming frame. Otherwise, byte pattern-offset + j is ignored.

TABLE 4-49:

FILTER I COMMAND BIT DEFINITIONS

Filter i Commands

Bits

Description

3:2

Address Type: Defines the destination address type of the pattern.

00 = Pattern applies only to unicast frames.

10 = Pattern applies only to multicast frames.

X1 = Pattern applies to all frames that have passed the regular receive filter.

RESERVED

Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.

TABLE 4-50:

FILTER I OFFSET BIT DEFINITIONS

Filter i Offset Description

Bits

Description

7:0

Pattern Offset: The offset of the first byte in the frame on which CRC is checked for Wakeup Frame

recognition. The MAC checks the first offset byte of the frame for CRC and checks to determine

whether the frame is a Wakeup frame. Offset 0 is the first byte of the incoming frame's destination

address.

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