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KSZ8091RNA bảng dữ liệu(PDF) 9 Page - Microchip Technology |
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KSZ8091RNA bảng dữ liệu(HTML) 9 Page - Microchip Technology |
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9 / 62 page ![]() 2016 Microchip Technology Inc. DS00002275A-page 9 KSZ8091RNA/RND 2.1 Strap-In Options - KSZ8091RNA/RND The PHYAD[1:0] and PME_EN strap-in pins are latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] and PME_EN strap-in pins, shared pin with the RMII CRS_DV and RXER signals respectively, to be latched to the unintended high/ low state. In this case, an external pull-up (4.7 kΩ) or pull-down (1.0 kΩ) should be added on the PHYAD[1:0] and PME_EN strap-in pins to ensure that the intended value is strapped-in correctly. Note 2-4 Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. TABLE 2-2: STRAP-IN OPTIONS - KSZ8091RNA/RND Pin Number Pin Name Type Note 2-4 Description 15 PHYAD[1:0] Ipd/O The PHY Address is latched at the de-assertion of reset and is con- figurable to either one of the following two values: Pull-up = PHY Address is set to 00011b (3h) Pull-down (default) = PHY Address is set to 00000b (0h) PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after writ- ing a ‘1’ to Register 16h, Bit [9]. PHY Address bits [4:2] are set to 000 by default. 17 PME_EN Ipd/O PME Output for Wake-On-LAN Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 16h, Bit [15]. 23 ANEN_SPEED Ipu/O Auto-Negotiation Enable and Speed Mode Pull-up (default) = Enable Auto-Negotiation and set 100 Mbps Speed Pull-down = Disable Auto-Negotiation and set 10 Mbps Speed At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12] for Auto-Negotiation enable/disable, Register 0h, Bit [13] for the Speed select, and Register 4h (Auto-Negotiation Advertisement) for the Speed capability support. |
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