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SST12LF02 bảng dữ liệu(PDF) 16 Page - Microchip Technology |
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SST12LF02 bảng dữ liệu(HTML) 16 Page - Microchip Technology |
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16 / 17 page ![]() ©2015 DS-70005001D 01/15 16 2.4 GHz WLAN High-Gain, High-Efficiency FEM SST12LF02 Data Sheet Packaging Diagrams For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing C04-14018A Sheet 1 of 1 16-Lead Extremely Thin Quad Flatpack No-Leads (QXCE/F) - 3x3 mm Body [XQFN] 16-xqfn-3x3-QXC-1.0 Note: 1. Complies with JEDEC JEP95 MO-248, variant XEED-4 except external paddle nominal dimensions. 2. From the bottom view, the pin #1 indicator may be either a 45-degree chamfer or a half-circle notch. 3. The external paddle is electrically connected to the die back-side and to VSS. This paddle must be soldered to the PC board; it is requiresd to connect this paddle to the VSS of the unit. Connection of this paddle to any other voltage potential will result in shorts and electrical malfunction of the device. 4. Untoleranced dimensions are nominal target dimensions. 5. All linear dimensions are in millimeters (max/min). |
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