SST49LF016C datasheet(13/43 Pages) MICROCHIP

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DS20005029B

02/16

16 Mbit LPC Serial Flash

SST49LF016C

EOL Data Sheet

Firmware Memory Write Cycle

Figure 7: Firmware Memory Write Cycle Waveform

Table 5: Firmware Memory Write Cycle

Clock

Cycle

Field

Name

Field

Contents

LAD[3:0]1

1. Field contents are valid on the rising edge of the present clock cycle.

LAD[3:0]

Direction

Comments

START

1110

LFRAME# must be active (low) for the part to respond. Only the

last start field (before LFRAME# transitions high) will be recog-

nized. The START field contents (1110b) indicate a Firmware

Memory Write cycle.

IDSEL

0000 to

1111

Indicates which SST49LF016C device should respond. If the

IDSEL (ID select) field matches the value of ID[3:0], then that par-

ticular device will respond to the whole bus cycle.

3-9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory address.

YYYY is one nibble of the entire address. Addresses are trans-

ferred most-significant nibble first.

MSIZE

KKKK

The MSIZE field indicates how many bytes will be transferred

during multi-byte operations.

Device supports 1, 2, and 4 Bytes write with MSIZE = 0, 1, or 2,

and KKKK=0000b, 0001b, or 0010b.

11-A

DATA

ZZZZ

A=(10+2n+1); n = MSIZE

Least significant nibble entered first.

(A+1)

TAR0

1111

IN then

Float

In this clock cycle, the master has driven the bus to all ‘1’s and

then floats the bus prior to the next clock cycle. This is the first part

of the bus “turnaround cycle.” A=(10+2n+1); n = MSIZE

(A+2)

TAR1

1111

(float)

Float

then OUT

The SST49LF016C takes control of the bus during this cycle.

A=(10+2n+1); n = MSIZE

(A+3)

RSYNC

0000

OUT

During this clock cycle, the SST49LF016C generates a “ready

sync” (RSYNC) and outputs the values 0000, indicating that it has

received data or a flash command. A=(10+2n+1); n = MSIZE

(A+4)

TAR0

1111

OUT then

Float

In this clock cycle, the SST49LF016C drives the bus to all ‘1’s and

then floats the bus prior to the next clock cycle. This is the first part

of the bus “turnaround cycle”. A=(10+2n+1); n = MSIZE

(A+5)

TAR1

1111

(float)

Float

then IN

The host resumes control of the bus during this cycle.

A=(10+2n+1); n = MSIZE

T5.0 20005029

1237 F04.0

LFRAME#

LAD[3:0]

1110b

0000b

A[23:20] A[19:16]

A[3:0]

A[7:4]

A[11:8]

A[15:12]

MADDR

Start

IDSEL

MSIZE

LCLK

A[27:24]

0000b

RSYNC

TAR1

TAR0

TAR

D0[7:4]

Tri-State

D0[3:0]

Dn[7:4]

Dn[3:0]

KKKKb

1111b

DATA

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