USB82640 datasheet(18/64 Pages) MICROCHIP

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USB82640

DS60001312A-page 18

 2010-2015 Microchip Technology Inc.

5.4

ROM BOOT Sequence

After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid signature of

2DFU

(device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is

enabled and code execution begins at address 0x0000 in the external SPI device. Otherwise, code execution continues

from the internal ROM.

If there is no SPI ROM detected, the internal firmware then checks for the presence of an I2C ROM. The firmware looks

for the signature ata2 at the offset of FCh-FFh and ecf1 at the offset of 17Ch-17Fh in the I2C ROM. The firmware

reads in the I2C ROM to configure the hardware and software internally. See Section 7.3.2, "EEPROM Data Descriptor,"

on page 22 for configuration options details.

The SPI ROM required for the USB82640 is a recommended minimum of 1 Mbit and support 60 MHz. The frequency

used is set using the SPI_SPD_SEL. For 60 MHz operation, this pin must pulled up through a 100 kΩ resistor. SPI_SP-

D_SEL is used to choose the speed of the SPI interface. During RESET_N assertion, this pin will be tri-stated with the

weak pull-down resistor enabled. When RESET_N is negated, the value on the pin will be internally latched, and the pin

will revert to SPI_DO functionality, and the internal pull-down is disabled.

The firmware can determine the speed of operation on the SPI port by checking the SPI_SPEED in the SPI_CTL Register

(0x2400 - RESET = 0x02). Both 1- and 2-bit SPI operation is supported. For optimum throughput, a 2-bit SPI ROM is

recommended. Both mode 0 and mode 3 SPI ROMS are also supported.

FIGURE 5-4:

SPI ROM CONNECTION

FIGURE 5-5:

I2C CONNECTION

SPI ROM

SPI_CE_N

SPI_CLK / SCL

SPI_DI

SPI_DO / SDA / SPI_SPD_SEL

USB82640

CE#

CLK

I2C ROM

SCL

SDA

3.3 V

10k

USB82640

10k

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