SSRAM

AS5SS256K36

AS5SS256K36

Rev. 4.4 10/13

Micross Components reserves the right to change products or specifications without notice.

3

PIN DESCRIPTION

Pin Number

SYMBOL

TYPE

DESCRIPTION

37

36

32-35, 44-50,

81, 82, 99,

100

43

SA0

SA1

SA

Input

Synchronous Address Inputs: These inputs are registered and must meet

the setup and hold times around the rising edge of CLK. Two different

pinouts are available for the TQFP packages.

93

94

95

96

BWa\

BWb\

BWc\

BWd\

Input

Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold times

around the rising edge of CLK. A byte write enable is LOW for a WRITE

cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;

Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;

Bwd\ controls DQd pins and DQPd. Parity bits are featured on this

device.

87

BWE\

Input

Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold items around the rising

edge of CLK.

88

GW\

Input

Global Write: This active LOW input allows a full 36-bit WRITE to occur

independent of the BWE\ and BWx\ lines and must meet the setup and

hold times around the rising edge of CLK.

89

CLK

Input

Clock: CLK registers address, data, chip enable, byte write enables and

burst control inputs on its rising edge. All synchronous inputs must meet

setup and hold times around the clock's rising edge.

98

CE\

Input

Synchronous Chip Enable: This active LOW input is used to enable the

device and conditions the internal use of ADSP\. CE\ is sampled only

when a new external address is loaded.

92

CE2\

Input

Synchronous Chip Enable: This active LOW input is used to enable the

device and is sampled only when a new external address is loaded.

97

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to enable the

device and is sampled only when a new external address is loaded.

86

OE\

Input

Output Enable: This active LOW, asynchronous input enables the data

I/O output drivers.

83

ADV\

Input

Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after the

external address is loaded. A HIGH on this pin effectively causes wait

states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV\ must be HIGH at the rising edge of

the first clock after an ADSP\ cycle is initiated.

85

ADSC\

Input

Synchronous Address Status Controller: This active LOW input interrupts

any ongoing burst, causing a new external address to be registered. A

READ or WRITE is performed using the new address if CE\ is LOW.

ADSC\ is also used to place the chip into power-down state when CE\ is

HIGH.