SSRAM

AS5SS256K36

AS5SS256K36

Rev. 4.4 10/13

Micross Components reserves the right to change products or specifications without notice.

2

GENERAL DESCRIPTION (continued)

Asynchronous inputs include the output enable (OE\),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode input (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE\, is also

asynchronous. WRITE cycles can be from one to four bytes

wide as controlled by the write control inputs.

Burst operation can be initiated with either address

status processor (ADSP\) or address status controller (ADSC\)

inputs. Subsequent burst addresses can be internally generated

as controlled by the burst advance input (ADV\).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE cycles.

Individual byte enables allow individual bytes to be written.

During WRITE cycles on the x18 device, BWa\ controls DQa’s

and DQPa; BWb\ controls DQb’s and DQPb; BWc\ controls

DQc’s and DQPc; BWd\ controls DQd’s and DQPd. GW\ LOW

causes all bytes to be written. Parity bits are also featured on

this device.

This 8Mb Synchronous Burst SRAM operates from a

+3.3V V

DD

power supply, and all inputs and outputs are TTL-

from a wide synchronous data bus.

18

18

16

18

SA0, SA1, SAs

SA0-SA1

MODE

ADV\

CLK

SA1'

SA0'

BWd\

BWc\

DQs

DQPa

DQPb

DQPc

BWb\

DQPd

BWa\

BWE\

GW\

OE\

ADDRESS

REGISTER

BINARY

COUNTER

AND LOGIC

Q1

Q0

CL

ADSC\

ADSP\

BYTE "d"

WRITE REGISTER

BYTE "c"

WRITE REGISTER

BYTE "b"

WRITE REGISTER

BYTE "a"

WRITE REGISTER

ENABLE

REGISTER

CE\

CE2

CE2\

BYTE "d"

WRITE DRIVER

BYTE "c"

WRITE DRIVER

BYTE "b"

WRITE DRIVER

BYTE "a"

WRITE DRIVER

256K x 9 x 4

(x36)

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

4

FUNCTIONAL BLOCK DIAGRAM

NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions

and time diagrams

for detailed information.