SSRAM

AS5SP512K36

AS5SP512K36

Rev. 3.0 10/13

Micross Components reserves the right to change products or specifications without notice.

3

Micross Components AS5SP512K36 Synchronous SRAM is

manufactured to support today’s High Performance platforms

utilizing the industry’s leading processor elements including

those of Intel and Motorola. The AS5SP512K36 supports

Synchronous SRAM READ and WRITE operations as well as

Synchronous Burst READ/WRITE operations. All inputs with

the exception of OE\, MODE and ZZ are synchronous in nature

and registered on the rising edge of input clock (CLK). The

type, start and duration of Burst Mode operations is controlled

by MODE, ADSC\, ADSP\ and ADV\. All synchronous

accesses, including the Burst accesses, are enabled via the use

of the multiple enable pins, and wait state insertion is supported

and controlled via the use of the Address Advance (ADV\).

The AS5SP512K36 supports both Interleaved and Linear Burst

modes.

The AS5SP512K36 supports Byte WRITE operations via the

Byte Write Enable (BWE\) and the Byte Write Select pin(s)

(BWa\, BWb\, BWc\, BWd\). Global Writes are supported

via the Global Write Enable (GW\). Global Write Enable will

override the Byte Write inputs and will perform a Write to all

36 Data Bits.

The AS5SP512K36 provides ease of producing very

dense arrays via the multiple Chip Enable input pins and

Asynchronous Output Enable.

Single Cycle Access Operations

A Single READ operation is initiated at the rising edge of Clock

when all of the following conditions are satisfied: [1] ADSP\

or ADSC\ is asserted LOW, [2] Chip Enables are all asserted

active, and [3] the WRITE signals (GW\, BWE\) are HIGH.

ADSP\ is ignored if CE1\ is HIGH. The address presented to

the Address inputs is stored within the Address Registers and

Address Counter/Advancement Logic and presented to the

array core. The corresponding data of the addressed location

is propagated to the Output Registers and passed to the data

bus on the next rising clock via the Output Buffers. The time

at which the data is presented to the Data bus is as specified

by either the Clock to Data valid specification or the Output

Enable to Data Valid spec for the device speed grade chosen.

The only exception occurs when the device is emerging from

a deselected to selected state where its outputs are tristated in

the first machine cycle and controlled by its Output Enable

(OE\) on following

cycle. Consecutive single cycle READS are supported. Once

the SRAM is deselected by use of the Chip Enable(s) and either

ADSP\ or ADSC\, its outputs will tri-state immediately.

A Single ADSP\ controlled WRITE operation is initiated when

both of the following conditions are satisfied at the rising edge

of Clock: [1] ADSP\ is asserted LOW, and [2] Chip Enable(s)

are asserted ACTIVE. The WRITE controls: Global Write,

Byte Write Enable (GW\, BWE\) the individual Byte Writes

(BWa\, BWb\, BWc\, BWd\), and ADV\ are ignored on the

first machine cycle. ADSP\ triggered WRITE accesses require

two (2) machine cycles to complete. If Global Write is asserted

LOW on the second Clock (CLK) rise, data will be written into

the selected address location. If GW\ is HIGH (inactive) then

the WRITE operation is controlled by BWE\ and one or more

of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\).

All WRITES that are initiated in this device are internally self

timed.

A Single ADSC\ controlled WRITE operation is initiated at

the rising edge of Clock when the following conditions are

satisfied: [1] ADSC\ is asserted LOW, [2] ADSP\ is de-asserted

(HIGH), [3] Chip Enable(s) are asserted (TRUE or Active),

and [4] the appropriate combination of the WRITE inputs

(GW\, BWE\, BWx\) are asserted (ACTIVE). ADSC\ triggered

WRITE accesses require a single clock (CLK) machine cycle

to complete. The ADV\ pin is ignored during this cycle.

Deep Power-Down Mode (SLEEP)

The AS5SP512K36 has a Deep Power-Down mode and is

controlled by the Asynchronous ZZ pin. Two clock cycles are

required to enter into or exit from this “sleep” mode. While

in this mode, Data integrity is guaranteed. For the device to

be placed successfully into this operational mode the device

must be deselected and the Chip Enables, ADSP\ and ADSC\

remain inactive for the duration of tZZREC after the ZZ input

returns LOW. Accesses pending when entering “sleep” mode

are not considered valid.

Functional Description