SSRAM

AS5SP512K36

AS5SP512K36

Rev. 3.0 10/13

Micross Components reserves the right to change products or specifications without notice.

2

ADDRESS

REGISTER

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

Q1

Q0

ADSP

ADSC

MODE

BWE

GW

OE

ENABLE

REGISTER

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

E

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

MEMORY

ARRAY

DQs

SLEEP

CONTROL

ZZ

2

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

BYTE

WRITE DRIVER

BYTE

WRITE DRIVER

BYTE

WRITE DRIVER

Pin Descriptions

Low order, synchronous address inputs and burst counter

address inputs.

35, 34, 33, 32, 100,

99, 82, 81, 44, 45, 46,

47, 48, 49, 50, 43, 42

Chip Enable

CE1\, CE3\

Sync Input

98, 92

Active low chip enables.

Chip Enable

CE2

Sync Input

97

Active high chip enable.

Global Write Enable

GW\

Sync Input

88

Active low global write enable. Write to all bits.

BWa\, BWb\,

BWc\, BWd\

Byte Write Enable

BWE\

Sync Input

87

Active low byte write function enable.

Output Enable

OE\

Input

86

Active low asynchronous output enable.

Asynchronous, non-time critical Power-down Input control. Places

the chip into an ultra low power mode, with data preserved.

52, 53, 56, 57, 58, 59,

62, 63, 68, 69, 72, 73,

74, 75, 78, 79, 2, 3, 6,

7, 8, 9, 12, 13, 18, 19,

22, 23, 24, 25, 28, 29

Burst Mode

MODE

Input

31

Interleaved or linear burst mode control.

Power Supply [Core]

VDD

Supply

91, 15, 41, 65

Core power supply.

Ground [Core]

VSS

Supply

90, 17, 40, 67

Core power supply ground.

4, 11, 20, 27, 54, 61,

70, 77

5, 10, 21, 26, 55, 60,

71, 76

Address Advance

Power-Down

DQPa, DQPb,

DQPc, DQPd

Synchronous clock.

When asserted LOW, address is captured in the address registers and A0-

A1 are loaded into the burst counter when ADSP\ and ADSC\ are both

asserted, only ADSP\ is recognized.

When asserted LOW, address is captured in the address registers, A0-A1

is registered in the burst counter. When both ADSP\ and ADSC\ or both

asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH.

When asserted LOW, address in burst counter is incremented on rising

edge of clock.

Synchronous parity on input/output.

Isolated input/output buffer ground.

Isolated input/output buffer supply.

DQa, DQb, DQc,

DQd

Sync

Input/

Output

Sync

Input/

Output

Synchronous data input/output.

No Connection(s)

NC

NA

No connections to internal silicon.

14, 16, 38, 39, 66

Data Input/Outputs

Supply

Supply

VDDQ

VSSQ

I/O Ground

CLK

Input

89

37, 36

Clock

93, 94, 95, 96

Active low byte write enables. Write to byte segments.

Byte Enables

Address

Address

A0, A1

A

Synchronous address inputs

Power Supply I/O

Address Status Processor

Address Status Controller

ADSC\

85

84

ADSP\

Sync Input

Sync Input

83

ADV\

ZZ

Input

64

51, 80, 1, 30

Data Parity Input/Outputs

Sync Input

Sync

Input(s)

Sync Input

Sync Input

Logic Block Diagram