AS4SD16M16 datasheet(19/52 Pages) MICROSS

19 / 52 page

SDRAM

AS4SD16M16

Rev. 2.6 04/13/15

Micross Components reserves the right to change products or specifications without notice.

CLOCK SUSPEND

The clock suspend mode occurs when a column access/

burst is in progress and CKE is registered LOW. In the clock

suspend mode, the internal clock is deactivated, “freezing” the

synchronous logic.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended. Any

command or data present on the input pins at the time of a

suspected internal clock edge is ignored; any data present on

the DQ pins remains driven; and burst counters are not incre-

mented, as long as the clock is suspended. (See examples in

Figure 22 and 23).

Clock suspend more is exited by registering CKE HIGH;

the internal clock and related operation will resume on the

subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by program-

ming the write burst mode bit (M9) in the mode register to a

logic 1. In this mode, all WRITE commands result in the access

of a single column location (burst of one), regardless of the

programmed burst length. READ commands access columns

according to the programmed burst length and sequence, just

as in the normal mode of operation (M9 = 0).

FIGURE 22: Clock Suspend During WRITE Burst

FIGURE 23: Clock Suspend During READ Burst

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