AS4SD8M16 datasheet(8/52 Pages) MICROSS

8 / 52 page

SDRAM

AS4SD8M16

Rev. 1.6 March 27, 2015

Micross Components reserves the right to change products or specifications without notice.

WRITE (continued)

selects the bank, and the address provided on inputs A0-A8

selects the starting column location. The value on input A10

determines whether or not auto precharge is used. If auto pre-

charge is selected, the row being accessed will be precharged at

the end of the WRITE burst; if auto precharge is not selected,

the row will remain open for subsequent accesses. Input data

appearing on the DQs is written to the memory array subject to

the DQM input logic level appearing coincident with the data.

If a given DQM signal is registered LOW, the corresponding

data will be written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs will be ignored, and a

WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open

row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row access a

specified time (t

RP) after the PRECHARGE command is issued.

Input A10 determines whether one or all banks are to be pre-

charged, an in the case where only one bank is to be precharged,

inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are

treated as “Don’t Care.” Once a bank has been precharged, it

is in the idle state and must be activated prior to any READ or

WRITE commands being issued to that bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the same individ-

ual-bank PRECHARGE functions described above, without

requiring an explicit command. This is accomplished by using

A10 to enable auto precharge in conjunction with a specific

READ or WRITE command. A PRECHARGE of the bank/

row that is addressed with the READ or WRITE command

is automatically performed upon completion of the READ or

WRITE burst, except in the full-page burst mode, whereAUTO

PRECHARGE does not apply. Auto precharge is nonpersistent

in that it is either enabled or disabled for each individual READ

or WRITE command.

Auto precharge ensures that the precharge is initiated at

the earliest valid stage within a burst. The user must not issue

another command to the same bank until the precharge time

RP) is completed. This is determined as if an explicit PRE-

CHARGE command was issued at the earliest possible time,

as described for each burst type in the Operation section of this

data sheet.

BURST TERMINATE

The BURST TERMINATE command is used to truncate

either fixed-length or full-page bursts. The most recently

registered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in the

Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the

SDRAM and is analogous to CAS\-BEFORE-RAS\ (CBR)

REFRESH in conventional DRAMs. This command is non-

persistent, so it must be issued each time a refresh is required.

All active banks must be precharged prior to issuing an AUTO

REFRESH command. The AUTO REFRESH command

should not be issued until the minimum t

RP has been met after

the PRECHARGE command as shown in the Operations sec-

tion.

The addressing is generated by the internal refresh con-

troller. This makes the address bits “Don’t Care” during an

AUTO REFRESH command. The 128Mb SDRAM requires

4,096 AUTO REFRESH cycles every 64ms (t

REF), regardless

of width operation. Providing a distributed AUTO REFRESH

command every 15.625µs will meet the refresh requirement and

ensure that each row is refreshed. Alternatively, 4,096 AUTO

REFRESH commands can be issued in a burst at the minimum

cycle rate (t

RFC), once every 64ms (24ms for XT version).

SELF REFRESH (IT & ET Temp options ONLY)

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is powered

down. When in the self refresh mode, the SDRAM retains data

without external clocking. The SELF REFRESH command is

initiated like and AUTO REFRESH command except CKE

is disabled (LOW). Once the SELF REFRESH command is

registered, all the inputs to the SDRAM become “Don’t Care”

with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides

its own internal clocking, causing it to perform its own AUTO

REFRESH cycles. The SDRAM must remain in self refresh

mode for a minimum period equal to tRAS and may remain in

self refresh mode for an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence

of commands. First, CLK must be stable (stable clock is de-

fined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. Once CKE

is HIGH, the SDRAM must have NOP commands issued (a

minimum of two clocks) for tXSR because time is required for

the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH

commands must be issued every 15.625µs or less as both

SELF REFRESH andAUTO REFRESH utilize the row refresh

counter. The SELF REFRESH and AUTO REFRESH option

are available with the IT and ET temperature options. They

are not available with the XT temperature options.

AS4SD8M16 bảng dữ liệu(PDF) 8 Page - Micross Components

AS4SD8M16 bảng dữ liệu(HTML) 8 Page - Micross Components

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

bảng dữ liệu tải về

Link URL