STM32F334X4 datasheet(95/115 Pages) STMICROELECTRONICS

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STM32F334x4 STM32F334x6 STM32F334x8

Electrical characteristics

100

DNL(3)

Differential non linearity

Difference between two

consecutive code-1LSB)

Given for a 10-bit input code

DAC1 channel 1

±0.5

LSB

Given for a 12-bit input code

DAC1 channel 1

±2

LSB

Given for a 10-bit input code

DAC1 channel 2 & DAC2 channel 1

-0.75/+0.25 LSB

Given for a 12-bit input code

DAC1 channel 2 & DAC2 channel 1

-3/+1

LSB

INL(3)

Integral non linearity

(difference between

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 4095)

Given for a 10-bit input code

±1

LSB

Given for a 12-bit input code

±4

LSB

Offset(3)

Offset error

(difference between

measured value at Code

(0x800) and the ideal value

= VDDA/2)

±10

Given for a 10-bit input code at

VDDA = 3.6 V

±3

LSB

Given for a 12-bit input code

±12

LSB

Gain

error(3)

Gain error

Given for a 12-bit input code

±0.5

tSETTLING(3

)

Settling time (full scale: for

a 12-bit input code

transition between the

lowest and the highest input

codes when DAC_OUT

reaches final value ±1LSB

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

-3

µs

Update

rate(3)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to

i+1LSB)

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

MS/

Iskink

Output sink current

DAC buffer ON

Output level higher than 0.2 V

100

µA

tWAKEUP(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

-6.5

µs

PSRR+ (1)

Power supply rejection ratio

(to VDDA) (static DC

measurement

No RLOAD, CLOAD = 50 pF

–67

–40

1. Guaranteed by design, not tested in production.

2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is

involved.

3. Data based on characterization results, not tested in production.

Table 69. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

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