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STM32F318C8 bảng dữ liệu(PDF) 14 Page - STMicroelectronics |
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STM32F318C8 bảng dữ liệu(HTML) 14 Page - STMicroelectronics |
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14 / 125 page ![]() Functional overview STM32F318C8 STM32F318K8 14/125 DocID026294 Rev 5 3.5.3 Low-power modes The STM32F318x8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx, I2C or USARTx. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop. 3.6 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Table 3. STM32F318x8 peripheral interconnect matrix Interconnect source Interconnect destination Interconnect action TIMx TIMx Timers synchronization or chaining ADC1 DAC1 Conversion triggers DMA Memory to memory transfer trigger Compx Comparator output blanking COMPx TIMx Timer input: OCREF_CLR input, input capture ADC1 TIM1 Timer triggered by analog watchdog GPIO RTCCLK HSE/32 MC0 TIM16 Clock source used as input channel for HSI and LSI calibration CSS CPU (hard fault) COMPx PVD GPIO TIM1 TIM15, 16, 17 Timer break |
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