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PM6344 bảng dữ liệu(PDF) 69 Page - PMC-Sierra, Inc |
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PM6344 bảng dữ liệu(HTML) 69 Page - PMC-Sierra, Inc |
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69 / 256 page ![]() STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 56 Register 001H, 081H, 101H, 181H: Receive Backplane Options Bit Type Function Default Bit 7 R/W RCLKOSEL 0 Bit 6 Unused X Bit 5 R/W RXDMAGAT 0 Bit 4 R/W ROHM 0 Bit 3 R/W BRX2RAIL 0 Bit 2 R/W BRXSMFP 0 Bit 1 R/W BRXCMFP 0 Bit 0 R/W OOSMFAIS 0 This register allows software to configure the Receive backplane interface format. RCLKOSEL: The RCLKOSEL bit selects the source of the RCLKO[x] output and the internal elastic store output clock. If RCLKOSEL is a logic zero, RCLKO[x] is the recovered clock derived from RDP[x] and RDN[x] or RCLKI[x] and the internal elastic store output clock is BRCLK. If RCLKOSEL is a logic one, RCLKO[x] and the internal elastic store output clock originate from the smooth 2.048 MHz clock generated by the DJAT phase locked loop. If the recovered clock is selected as the PLL reference, the configuration implements jitter attenuation in the receive direction. See the Operations Section for details on this application. TRSLIP must be set to logic 0. RXDMAGAT: The RXDMAGAT bit selects the gating of the RDLINT[x] output with the RDLEOM[x] output when the internal HDLC receiver is used with DMA. When RXDMAGAT is set to logic 1, the RDLINT[x] DMA output is gated with the RDLEOM[x] output so that RDLINT[x] is forced to logic 0 when RDLEOM[x] is logic 1. When RXDMAGAT is set to logic 0, the RDLINT[x] and RDLEOM[x] outputs operate independently. BRX2RAIL: The BRX2RAIL bit selects whether the backplane receive data signal on the multifunction outputs BRPCM/BRDP[x] and BRSIG/BRDN[x] are in either dual |
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