PM6344 datasheet(67/256 Pages) PMC

67 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

and the transmit clock driving the TRAN block when the ELST is bypassed.

When TRSLIP is set to logic 1, the transmit clock input to TRAN is internally

substituted for the BRCLK input to the system side of the ELST. When

TRSLIP is set to logic 0, the BRCLK input is routed to the system side of the

ELST. The TRSLIP bit should only be set if ELSTBYP is set to logic 1.

SRSMFP, SRCMFP:

The SRSMFP and SRCMFP bits select the output signal seen on the output

RFP[x]. RFP[x] can be used to show the frame alignment when fractional E1

extraction is being used (RFRACE1 is set to logic 1 in the DataLink Options

registers). The following table summarizes the four configurations:

SRSMFP

SRCMFP

Result

Receive frame pulse output:

RFP[x] pulses high for 1 RCLKO[x] cycle during bit

1 of each 256-bit frame, indicating the frame

alignment of the RDLSIG[x] fractional E1 data

stream.

Receive CRC multiframe output:

RFP[x] pulses high for 1 RCLKO[x] cycle during bit

1 of frame 1 of every 16 frame CRC multiframe,

indicating the CRC multiframe alignment of the

RDLSIG[x] fractional E1 data stream. (Even when

CRC multiframing is disabled, the RFP[x] output

continues to indicate the position of bit 1 of the FAS

frame every 16th frame.)

Receive signaling multiframe output:

RFP[x] pulses high for 1 RCLKO[x] cycle during bit

1 of frame 1 of the 16 frame signaling multiframe,

indicating the signaling multiframe alignment of the

RDLSIG[x] fractional E1 data stream. (Even when

signaling multiframing is disabled, the RFP[x] output

continues to indicate the position of bit 1 of every

16th frame.)

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