TMS320DM642 datasheet(21/178 Pages) TI

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2.5.2

Signal Groups Description

TRST

GP0[7]/EXT_INT7(B)

IEEE Standard

1149.1

(JTAG)

Emulation

Reserved

Reset and

Interrupts

Control/Status

TDI

TDO

TMS

TCK

EMU0

EMU1

NMI

GP0[6]/EXT_INT6(B)

GP0[5]/EXT_INT5(B)

GP0[4]/EXT_INT4(B)

RESET

RSV07

RSV06

Clock/PLL

CLKIN

CLKMODE1

CLKMODE0

PLLV

EMU2

EMU3

EMU4

EMU5

GP0

General-Purpose Input/Output 0 (GP0) Port

GP0[7]/EXT_INT7(B)

GP0[6]/EXT_INT6(B)

GP0[5]/EXT_INT5(B)

GP0[4]/EXT_INT4(B)

GP0[3]/PCIEEAI

CLKOUT6/GP0[2](A)

CLKOUT4/GP0[1](A)

GP0[0]

CLKOUT6/GP0[2](A)

CLKOUT4/GP0[1](A)

EMU6

EMU7

EMU8

EMU9

EMU10

GP0[15]/PRST(C)

GP0[14]/PCLK(C)

GP0[13]/PINTA (C)

GP0[12]/PGNT(C)

GP0[11]/PREQ(C)

GP0[10]/PCBE3(C)

GP0[9]/PIDSEL(C)

VDAC/GP0[8]/PCI66(C)

RSV08

EMU11

RSV04

RSV03

RSV05

Peripheral

Control/Status

PCI_EN

TOUT0/MAC_EN

RSV01

RSV00

RSV02

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6).

To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly

enabled and configured. For more details, see the Device Configurations section of this data sheet.

These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is

EXT_INTx or GPIO as input-only.

These GP0 pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with

both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations

section of this data sheet.

Figure 2-7. CPU and Peripheral Signals

Device Overview

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