CS89712 datasheet(152/170 Pages) CIRRUS

152 / 170 page

CS89712

152

DS502PP2

tNCSRD

tPCSRD

tADRD

Data in

Bus held

Data in

eXPCLK

nCS[5:0]

nMOE

A[27:0]

WORD

D[31:0]

eXPRDY

Figure 24. Consecutive Memory Read Cycles with Minimum Wait States

Notes: 1. tnCSRD = 50 ns at 36.864 MHz

70 ns at 18.432 MHz

Maximum values for minimum wait states. This time can be extended by integer multiples of the clock

period (27 ns at 36 MHz or 54 ns at 18.432 MHz), by either driving EXPRDY low and/or by

programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before

the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is

sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

2. Consecutive reads with sequential access enabled are identical except that the sequential access

wait state field is used to determine the number of wait states, and no idle cycles are inserted

between successive non-sequential ROM/expansion cycles. This improves performance so the

SQAEN bit should always be set where possible.

tnCSRD = tADRD = tPCSRD

4. When the CS89712 device implements consecutive reads(e.g., use of the LDM instruction),

regardless of the state of the SQAEN bit, the signals nMOE and nCSx will always remain low through

the entire multi-read access. They will not toggle in-between each different address access. In order

to have these signals toggle, single access read instructions (e.g., LDR) must be used.

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