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CS89712 bảng dữ liệu(PDF) 69 Page - Cirrus Logic |
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CS89712 bảng dữ liệu(HTML) 69 Page - Cirrus Logic |
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69 / 170 page  CS89712 DS502PP2 69 Address Name Default RD/WR Size Comments 0x8000.0000 PADR 0 RW 8 Port A data register. 0x8000.0001 PBDR 0 RW 8 Port B data register. 0x8000.0002 — — 8 Reserved. 0x8000.0003 PDDR 0 RW 8 Port D data register. 0x8000.0040 PADDR 0 RW 8 Port A data direction register. 0x8000.0041 PBDDR 0 RW 8 Port B data direction register. 0x8000.0042 — — 8 Reserved. 0x8000.0043 PDDDR 0 RW 8 Port D data direction register. 0x8000.0080 PEDR 0 RW 3 Port E data register. 0x8000.00C0 PEDDR 0 RW 3 Port E data direction register. 0x8000.0100 SYSCON1 0 RW 32 System control register 1. 0x8000.0140 SYSFLG1 0 RD 32 System status flags register 1. 0x8000.0180 MEMCFG1 0 RW 32 Expansion memory configuration register 1. 0x8000.01C0 MEMCFG2 0 RW 32 Expansion memory configuration register 2. 0x8000.0200 0 RW 32 Reserved. 0x8000.0240 INTSR1 0 RD 32 Interrupt status register 1. 0x8000.0280 INTMR1 0 RW 32 Interrupt mask register 1. 0x8000.02C0 LCDCON 0 RW 32 LCD control register. 0x8000.0300 TC1D 0 RW 16 Read / Write register sets and reads data to TC1. 0x8000.0340 TC2D 0 RW 16 Read / Write register sets and reads data to TC2. 0x8000.0380 RTCDR — RW 32 Real Time Clock data register. 0x8000.03C0 RTCMR — RW 32 Real Time Clock match register. 0x8000.0400 PMPCON 0 RW 12 PWM pump control register. 0x8000.0440 CODR 0 RW 8 CODEC data I/O register. 0x8000.0480 UARTDR1 0 RW 16 UART1 FIFO data register. 0x8000.04C0 UBLCR1 0 RW 32 UART1 bit rate and line control register. 0x8000.0500 SYNCIO 0 RW 32 Synchronous serial I/O data register for master only SSI. 0x8000.0540 PALLSW 0 RW 32 Least significant 32-bit word of LCD palette register. 0x8000.0580 PALMSW 0 RW 32 Most significant 32-bit word of LCD palette register. 0x8000.05C0 STFCLR — WR — Write to clear all start up reason flags. 0x8000.0600 BLEOI — WR — Write to clear battery low interrupt. 0x8000.0640 MCEOI — WR — Write to clear media changed interrupt. 0x8000.0680 TEOI — WR — Write to clear tick and watchdog interrupt. 0x8000.06C0 TC1EOI — WR — Write to clear TC1 interrupt. 0x8000.0700 TC2EOI — WR — Write to clear TC2 interrupt. 0x8000.0740 RTCEOI — WR — Write to clear RTC match interrupt. Table 31. CS89712 Internal Registers (Little Endian Mode) |
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