CS8420 datasheet(51/80 Pages) CIRRUS

51 / 80 page

CS8420

DS245PP2

14.2.1

Pin Description - Hardware Mode 1

Overall Device Control:

DFC0, DFC1 - Data Flow Control Inputs

DFC0 and DFC1 inputs determine the major data flow options available in hardware mode, according to

Table 3.

S/AES - Serial Audio or AES3 Input Select

S/AES is connected to ground in hardware mode 1, in order to select the AES3 input.

MUTE - Mute Output Data Input

If MUTE is low, audio data is passed normally. If MUTE is high, then both the AES3 transmitted audio

data and the serial audio output port data is set to digital zero.

OMCK - Output Section Master Clock Input

Output section master clock input. The frequency must be 256x the output sample rate (Fso).

AES3/SPDIF Receiver Interface:

RXP, RXN - Differential Line Receiver Inputs

Differential line receiver inputs, carrying AES3 type data.

RMCK - Input Section Recovered Master Clock Output

Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).

This is also a start-up option pin, and requires a pull-up or pull-down resistor.

RERR - Receiver Error Indicator

When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is

updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity

error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin,

and requires a pull-up or pull-down resistor.

EMPH/U - Pre-emphasis Indicator Output or U-bit Data Input

The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type

data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. When

indicating emphasis EMPH/U is low if the incoming data indicates 50/15

µs pre-emphasis and high

otherwise.

CS8420 bảng dữ liệu(PDF) 51 Page - Cirrus Logic