CL-PD6722 datasheet(4/128 Pages) CIRRUS

4 / 128 page

PRELIMINARY DATA SHEET v3.1

May 1997

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

14. DMA OPERATION

(CL-PD6722 only)................................ 83

14.1 DMA Capabilities of the CL-PD6722 ............... 83

14.2 DMA-Type PC Card Cycles ............................. 83

14.3 ISA Bus DMA Handshake Signal..................... 84

14.4 Conﬁguring the CL-PD6722 Registers for

a DMA Transfer ................................................ 84

14.4.1 Programming the DMA Request Pin from

the Card........................................................ 85

14.4.2 Conﬁguring the Socket Interface for I/O ....... 86

14.4.3 Preventing Dual Interpretation of DMA

Handshake Signals....................................... 86

14.4.4 Turning On DMA System .............................. 86

14.5 The DMA Transfer Process .............................. 86

14.6 Terminal Count to Card at Conclusion

of Transfer ....................................................... 86

15. ELECTRICAL SPECIFICATIONS ....... 87

15.1 Absolute Maximum Ratings ............................. 87

15.2 DC Speciﬁcations ............................................ 87

15.3 AC Timing Speciﬁcations ................................. 91

15.3.1 ISA Bus Timing ............................................. 92

15.3.2 Reset Timing................................................. 94

15.3.3 System Interrupt Timing................................ 95

15.3.4 General-Purpose Strobe Timing

(CL-PD6722 only) ......................................... 96

15.3.5 Input Clock Speciﬁcation .............................. 97

15.3.6 PC Card Bus Timing Calculations ................ 98

15.3.7 PC Card Socket Timing ................................ 99

16. PACKAGE SPECIFICATIONS........... 110

16.1 144-Pin VQFP Package ................................. 110

16.2 208-Pin PQFP Package ................................. 111

16.3 208-Pin VQFP Package ................................. 112

17. ORDERING INFORMATION

EXAMPLE .......................................... 113

Using the Cirrus Logic BBS

and FTP Server................................. 114

B.1

Operation Registers ....................................... 116

B.2

Chip Control Registers................................... 116

B.3

I/O Window Mapping Registers ..................... 118

B.4

Memory Window Mapping Registers ............. 119

B.5

Extension Registers ....................................... 120

B.6

Timing Registers ............................................ 123

INDEX ................................................ 124

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