MCP3918A1-ESLASHML datasheet(43/88 Pages) MICROCHIP

43 / 88 page

 2014 Microchip Technology Inc.

DS20005287A-page 43

MCP3918

6.0

SPI SERIAL INTERFACE

DESCRIPTION

6.1

Overview

The MCP3918 device includes a four-wire (CS, SCK,

SDI, SDO) digital serial interface that is compatible with

SPI Modes 0,0 and 1,1. Data is clocked out of the

MCP3918 on the falling edge of SCK, and data is

clocked into the MCP3918 on the rising edge of SCK.

In these modes, the SCK clock can idle either high (1,1)

or low (0,0). The digital interface is asynchronous with

the MCLK clock that controls the ADC sampling and

digital filtering. All the digital input pins are

Schmitt-triggered to avoid system noise perturbations

on the communications.

Each independent SPI communication starts with a CS

falling edge and stops with the CS rising edge. When

CS is logic high, SDO is in high-impedance, there are

transitions on SCK, and SDI has no effect. Changing

from an SPI Mode 1,1 to an SPI Mode 0,0 and vice

versa is possible and can be done while the CS pin is

logic

high.

Any

rising

edge

clears

the

communication and resets the SPI digital interface.

Additional control pins (RESET, DR) are also provided

on separate pins for advanced communication

features. The Data Ready pin (DR) outputs pulses

when a new ADC channel data is available for reading,

which can be used as an interrupt for an MCU. The

master reset pin (RESET) acts like a hard reset and

can reset the part to its default power-up configuration

(equivalent to a POR state).

The MCP3918 interface has a simple command

structure. Every command is either a Read command

from a register or a Write command to a register. The

MCP3918 device includes nine registers defined in the

compatible with the MCP391X family to allow easy

porting of MCU code from one design to another inside

the MCP391X family. The first byte (8-bit wide)

transmitted is always the Control byte that defines the

address of the register and the type of command (Read

or Write). It is followed by the register itself, which can

be in a 16-, 24- or 32-bit format, depending on the

multiple format settings defined in the STATUSCOM

formats that help reduce overhead in the data handling

for most MCUs and processors available on the market

(8-, 16- or 32-bit MCUs) and improve MCU-code

compaction and efficiency.

The MCP3918 digital interface is capable of handling

various continuous read and write modes, which allow

the device to perform ADC data streaming or full

(and therefore with only one unique Control byte). The

internal registers can be grouped together with various

configurations through the READ<1:0> and WRITE

bits. The internal address counter of the serial interface

can be automatically incremented with no additional

Control byte needed, in order to loop through the

various groups of registers within the register map. The

groups are defined in Table 9-2.

The MCP3918 device also includes advanced security

features to secure each communication, to avoid

processing unwanted write commands in order to

change the desired configuration, and to alert the user

in case of a change in the desired configuration.

Each SPI read communication can be secured through

a selectable CRC-16 checksum provided on the SDO

pin at the end of every communication sequence. This

CRC-16 computation is compatible with the DMA CRC

hardware of the PIC24 and PIC32 MCUs, resulting in

no additional overhead for added security.

In order to secure the entire configuration of the device,

the

MCP3918

includes

8-bit

lock

code

(LOCK<7:0>), which blocks all write commands to the

full register map if the value of the LOCK<7:0> is not

equal to a defined password (0xA5). The user can

protect its configuration by changing the LOCK<7:0>

value to 0x00 after the full programming, so that no

unwanted write command will result in a change in the

configuration (because LOCK<7:0> is different from

the 0xA5 password).

An additional CRC-16 calculation is also running

continuously in the background to ensure the integrity

of the full register map. All writable registers of the

processed through a CRC-16 calculation engine and

give a CRC-16 checksum that depends on the

configuration. This checksum is readable on the

LOCK/CRC register and updated at all times. If a

change in this checksum occurs, a selectable interrupt

can give a flag on the DR pin (the DR pin becomes logic

low) to warn the user that the configuration is

corrupted.

MCP3918A1-E/ML bảng dữ liệu(PDF) 43 Page - Microchip Technology

MCP3918A1-E/ML bảng dữ liệu(HTML) 43 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

bảng dữ liệu tải về

Link URL